ath9k: fix pll clock initialization on newer soc devices (fixes #14916)

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 42453

package/kernel/mac80211/patches/300-pending_work.patch

@@ -1,3 +1,23 @@
+commit 11f17631d9bf2a9e910dac7d09ba4581f5693831
+Author: Felix Fietkau <nbd@openwrt.org>
+Date:   Tue Sep 9 09:48:30 2014 +0200
+
+    ath9k_hw: fix PLL clock initialization for newer SoC
+    
+    On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL
+    register changed. This currently breaks at least 5/10 MHz operation.
+    AR933x uses the old layout.
+    
+    It might also have been causing other stability issues because of the
+    different location of the PLL_BYPASS bit which needs to be set during
+    PLL clock initialization.
+    
+    This patch also removes more instances of hardcoded register values in
+    favor of properly computed ones with the PLL_BYPASS bit added.
+    
+    Reported-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
+    Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
 commit 0fecedddd4a0945873db1bd230ec6a168b3cc4fe
 Author: Felix Fietkau <nbd@openwrt.org>
 Date:   Mon Sep 8 18:35:08 2014 +0200
@@ -3166,3 +3186,108 @@ Date:   Mon May 19 21:20:49 2014 +0200
  
  		if (level != aniState->spurImmunityLevel) {
  			ath_dbg(common, ANI,
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -517,6 +517,23 @@ static void ar9003_hw_spur_mitigate(stru
+ 	ar9003_hw_spur_mitigate_ofdm(ah, chan);
+ }
+ 
++static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
++					     struct ath9k_channel *chan)
++{
++	u32 pll;
++
++	pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
++
++	if (chan && IS_CHAN_HALF_RATE(chan))
++		pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
++	else if (chan && IS_CHAN_QUARTER_RATE(chan))
++		pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
++
++	pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
++
++	return pll;
++}
++
+ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
+ 					 struct ath9k_channel *chan)
+ {
+@@ -1779,7 +1796,12 @@ void ar9003_hw_attach_phy_ops(struct ath
+ 
+ 	priv_ops->rf_set_freq = ar9003_hw_set_channel;
+ 	priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
+-	priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
++
++	if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
++		priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
++	else
++		priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
++
+ 	priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
+ 	priv_ops->init_bb = ar9003_hw_init_bb;
+ 	priv_ops->process_ini = ar9003_hw_process_ini;
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -702,6 +702,8 @@ static void ath9k_hw_init_pll(struct ath
+ {
+ 	u32 pll;
+ 
++	pll = ath9k_hw_compute_pll_control(ah, chan);
++
+ 	if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
+ 		/* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
+ 		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
+@@ -752,7 +754,8 @@ static void ath9k_hw_init_pll(struct ath
+ 		REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
+ 			      AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
+ 
+-		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
++		REG_WRITE(ah, AR_RTC_PLL_CONTROL,
++			  pll | AR_RTC_9300_PLL_BYPASS);
+ 		udelay(1000);
+ 
+ 		/* program refdiv, nint, frac to RTC register */
+@@ -768,7 +771,8 @@ static void ath9k_hw_init_pll(struct ath
+ 	} else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
+ 		u32 regval, pll2_divint, pll2_divfrac, refdiv;
+ 
+-		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
++		REG_WRITE(ah, AR_RTC_PLL_CONTROL,
++			  pll | AR_RTC_9300_SOC_PLL_BYPASS);
+ 		udelay(1000);
+ 
+ 		REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
+@@ -840,7 +844,6 @@ static void ath9k_hw_init_pll(struct ath
+ 		udelay(1000);
+ 	}
+ 
+-	pll = ath9k_hw_compute_pll_control(ah, chan);
+ 	if (AR_SREV_9565(ah))
+ 		pll |= 0x40000;
+ 	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+--- a/drivers/net/wireless/ath/ath9k/reg.h
++++ b/drivers/net/wireless/ath/ath9k/reg.h
+@@ -1236,12 +1236,23 @@ enum {
+ #define AR_CH0_DPLL3_PHASE_SHIFT_S   23
+ #define AR_PHY_CCA_NOM_VAL_2GHZ      -118
+ 
++#define AR_RTC_9300_SOC_PLL_DIV_INT          0x0000003f
++#define AR_RTC_9300_SOC_PLL_DIV_INT_S        0
++#define AR_RTC_9300_SOC_PLL_DIV_FRAC         0x000fffc0
++#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S       6
++#define AR_RTC_9300_SOC_PLL_REFDIV           0x01f00000
++#define AR_RTC_9300_SOC_PLL_REFDIV_S         20
++#define AR_RTC_9300_SOC_PLL_CLKSEL           0x06000000
++#define AR_RTC_9300_SOC_PLL_CLKSEL_S         25
++#define AR_RTC_9300_SOC_PLL_BYPASS           0x08000000
++
+ #define AR_RTC_9300_PLL_DIV          0x000003ff
+ #define AR_RTC_9300_PLL_DIV_S        0
+ #define AR_RTC_9300_PLL_REFDIV       0x00003C00
+ #define AR_RTC_9300_PLL_REFDIV_S     10
+ #define AR_RTC_9300_PLL_CLKSEL       0x0000C000
+ #define AR_RTC_9300_PLL_CLKSEL_S     14
++#define AR_RTC_9300_PLL_BYPASS       0x00010000
+ 
+ #define AR_RTC_9160_PLL_DIV	0x000003ff
+ #define AR_RTC_9160_PLL_DIV_S   0

package/kernel/mac80211/patches/523-ath9k_use_configured_antenna_gain.patch

@@ -10,7 +10,7 @@
  
 --- a/drivers/net/wireless/ath/ath9k/hw.c
 +++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -2721,7 +2721,7 @@ void ath9k_hw_apply_txpower(struct ath_h
+@@ -2724,7 +2724,7 @@ void ath9k_hw_apply_txpower(struct ath_h
  	channel = chan->chan;
  	chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
  	new_pwr = min_t(int, chan_pwr, reg->power_limit);

package/kernel/mac80211/patches/542-ath9k_debugfs_diag.patch

@@ -94,7 +94,7 @@
  struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
 --- a/drivers/net/wireless/ath/ath9k/hw.c
 +++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -1735,6 +1735,20 @@ fail:
+@@ -1738,6 +1738,20 @@ fail:
  	return -EINVAL;
  }
  
@@ -115,7 +115,7 @@
  int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
  		   struct ath9k_hw_cal_data *caldata, bool fastcc)
  {
-@@ -1940,6 +1954,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+@@ -1943,6 +1957,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  		ar9003_hw_disable_phy_restart(ah);
  
  	ath9k_hw_apply_gpio_override(ah);

package/kernel/mac80211/patches/543-ath9k-allow-to-disable-bands-via-platform-data.patch

@@ -11,7 +11,7 @@
  	int (*external_reset)(void);
 --- a/drivers/net/wireless/ath/ath9k/hw.c
 +++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -2328,17 +2328,25 @@ int ath9k_hw_fill_cap_info(struct ath_hw
+@@ -2331,17 +2331,25 @@ int ath9k_hw_fill_cap_info(struct ath_hw
  	}
  
  	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);

package/kernel/mac80211/patches/550-ath9k_entropy_from_adc.patch

@@ -18,7 +18,7 @@
  	void (*spectral_scan_trigger)(struct ath_hw *ah);
 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-@@ -1764,6 +1764,26 @@ static void ar9003_hw_tx99_set_txpower(s
+@@ -1781,6 +1781,26 @@ static void ar9003_hw_tx99_set_txpower(s
  		  ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14],  0));
  }
  
@@ -45,7 +45,7 @@
  void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
  {
  	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-@@ -1794,6 +1814,7 @@ void ar9003_hw_attach_phy_ops(struct ath
+@@ -1816,6 +1836,7 @@ void ar9003_hw_attach_phy_ops(struct ath
  	priv_ops->set_radar_params = ar9003_hw_set_radar_params;
  	priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
  

package/kernel/mac80211/patches/551-ath9k-ar933x-usb-hang-workaround.patch

@@ -20,7 +20,7 @@
  /******************/
  /* Chip Revisions */
  /******************/
-@@ -1337,6 +1350,9 @@ static bool ath9k_hw_set_reset(struct at
+@@ -1340,6 +1353,9 @@ static bool ath9k_hw_set_reset(struct at
  	if (AR_SREV_9100(ah))
  		udelay(50);
  
@@ -30,7 +30,7 @@
  	return true;
  }
  
-@@ -1436,6 +1452,9 @@ static bool ath9k_hw_chip_reset(struct a
+@@ -1439,6 +1455,9 @@ static bool ath9k_hw_chip_reset(struct a
  		ar9003_hw_internal_regulator_apply(ah);
  	ath9k_hw_init_pll(ah, chan);
  
@@ -40,7 +40,7 @@
  	return true;
  }
  
-@@ -1730,8 +1749,14 @@ static int ath9k_hw_do_fastcc(struct ath
+@@ -1733,8 +1752,14 @@ static int ath9k_hw_do_fastcc(struct ath
  	if (AR_SREV_9271(ah))
  		ar9002_hw_load_ani_reg(ah, chan);
  
@@ -55,7 +55,7 @@
  	return -EINVAL;
  }
  
-@@ -1959,6 +1984,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+@@ -1962,6 +1987,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  	if (AR_SREV_9565(ah) && common->bt_ant_diversity)
  		REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
  

package/kernel/mac80211/patches/562-ath9k_ani_ws_detect.patch

@@ -79,7 +79,7 @@
  /**
   * ar9003_hw_set_channel - set channel on single-chip device
   * @ah: atheros hardware structure
-@@ -954,11 +940,6 @@ static bool ar9003_hw_ani_control(struct
+@@ -971,11 +957,6 @@ static bool ar9003_hw_ani_control(struct
  	struct ath_common *common = ath9k_hw_common(ah);
  	struct ath9k_channel *chan = ah->curchan;
  	struct ar5416AniState *aniState = &ah->ani;
@@ -91,7 +91,7 @@
  	s32 value, value2;
  
  	switch (cmd & ah->ani_function) {
-@@ -972,61 +953,6 @@ static bool ar9003_hw_ani_control(struct
+@@ -989,61 +970,6 @@ static bool ar9003_hw_ani_control(struct
  		 */
  		u32 on = param ? 1 : 0;
  

package/kernel/mac80211/patches/565-ath9k_restart_after_nfcal_failure.patch

@@ -152,7 +152,7 @@
  	unsigned int len = 0;
 --- a/drivers/net/wireless/ath/ath9k/link.c
 +++ b/drivers/net/wireless/ath/ath9k/link.c
-@@ -376,9 +376,14 @@ void ath_ani_calibrate(unsigned long dat
+@@ -371,9 +371,14 @@ void ath_ani_calibrate(unsigned long dat
  
  	/* Perform calibration if necessary */
  	if (longcal || shortcal) {

package/kernel/mac80211/patches/567-ath9k_fix_init_nfcal.patch

@@ -10,7 +10,7 @@
  		set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
 --- a/drivers/net/wireless/ath/ath9k/hw.c
 +++ b/drivers/net/wireless/ath/ath9k/hw.c
-@@ -1969,8 +1969,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
+@@ -1972,8 +1972,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  	if (ath9k_hw_mci_is_enabled(ah))
  		ar9003_mci_check_bt(ah);