ath79: fix QCA9557 eth PLL settings

The QCA9557 dtsi is currently missing pll-handle and pll-regs for both
eth0 and eth1, therefore PLL settings won't be applied. This commit
fixes this behavior.

Signed-off-by: David Bauer <mail@david-bauer.net>
master
David Bauer 6 years ago committed by John Crispin
parent 5107ba2374
commit 4b9680f138
  1. 8
      target/linux/ath79/dts/qca9557.dtsi

@ -109,7 +109,7 @@
pll: pll-controller@18050000 {
compatible = "qca,ar9557-pll",
"qca,qca9550-pll";
"qca,qca9550-pll", "syscon";
reg = <0x18050000 0x50>;
#clock-cells = <1>;
@ -295,6 +295,9 @@
&eth0 {
compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
pll-reg = <0 0x28 0>;
pll-handle = <&pll>;
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-mode = "rgmii";
@ -310,6 +313,9 @@
&eth1 {
compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
pll-reg = <0 0x48 0>;
pll-handle = <&pll>;
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-mode = "sgmii";

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