ipq806x: fix pcie reset gpio definions and move them to the common .dtsi file

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47544

target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

@@ -15,59 +15,59 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -35,6 +35,24 @@
+@@ -115,5 +115,15 @@
- 				bias-disable;
- 			};
- 
-+			pcie0_pins: pcie0_pinmux {
-+				mux {
-+					pins = "gpio3";
-+					function = "pcie1_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
-+			pcie1_pins: pcie1_pinmux {
-+				mux {
-+					pins = "gpio48";
-+					function = "pcie2_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
- 			spi_pins: spi_pins {
- 				mux {
- 					pins = "gpio18", "gpio19", "gpio21";
-@@ -115,5 +133,21 @@
  		usb30@1 {
  			status = "ok";
  		};
 +
 +		pcie0: pci@1b500000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 3 0>;
-+			pinctrl-0 = <&pcie0_pins>;
-+			pinctrl-names = "default";
 +			phy-tx0-term-offset = <7>;
 +		};
 +
 +		pcie1: pci@1b700000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 48 0>;
-+			pinctrl-0 = <&pcie1_pins>;
-+			pinctrl-names = "default";
 +			phy-tx0-term-offset = <7>;
 +		};
  	};
  };
 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -30,6 +30,33 @@
+@@ -128,5 +128,17 @@
- 				bias-disable;
+ 		usb30@1 {
- 			};
+ 			status = "ok";
+ 		};
++
++		pcie0: pci@1b500000 {
++			status = "ok";
++		};
++
++		pcie1: pci@1b700000 {
++			status = "ok";
++		};
++
++		pcie2: pci@1b900000 {
++			status = "ok";
++		};
+ 	};
+ };
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -3,6 +3,9 @@
+ #include "skeleton.dtsi"
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+ #include <dt-bindings/soc/qcom,gsbi.h>
++#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/gpio/gpio.h>
  
+ / {
+ 	model = "Qualcomm IPQ8064";
+@@ -83,6 +86,33 @@
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+ 			interrupts = <0 32 0x4>;
++
 +			pcie0_pins: pcie0_pinmux {
 +				mux {
 +					pins = "gpio3";
@@ -94,49 +94,10 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +					bias-disable;
 +				};
 +			};
-+
- 			spi_pins: spi_pins {
- 				mux {
- 					pins = "gpio18", "gpio19", "gpio21";
-@@ -128,5 +155,26 @@
- 		usb30@1 {
- 			status = "ok";
  		};
-+
-+		pcie0: pci@1b500000 {
-+			status = "ok";
-+			reset-gpio = <&qcom_pinmux 3 0>;
-+			pinctrl-0 = <&pcie0_pins>;
-+			pinctrl-names = "default";
-+		};
-+
-+		pcie1: pci@1b700000 {
-+			status = "ok";
-+			reset-gpio = <&qcom_pinmux 48 0>;
-+			pinctrl-0 = <&pcie1_pins>;
-+			pinctrl-names = "default";
-+		};
-+
-+		pcie2: pci@1b900000 {
-+			status = "ok";
-+			reset-gpio = <&qcom_pinmux 63 0>;
-+			pinctrl-0 = <&pcie2_pins>;
-+			pinctrl-names = "default";
-+		};
- 	};
- };
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -3,6 +3,8 @@
- #include "skeleton.dtsi"
- #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
- #include <dt-bindings/soc/qcom,gsbi.h>
-+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
  
- / {
+ 		intc: interrupt-controller@2000000 {
- 	model = "Qualcomm IPQ8064";
+@@ -311,6 +341,144 @@
-@@ -311,6 +313,129 @@
  			reg = <0x01200600 0x100>;
  		};
  
@@ -178,6 +139,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +				 <&gcc PCIE_PHY_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy";
 +
++			pinctrl-0 = <&pcie0_pins>;
++			pinctrl-names = "default";
++
++			perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
++
 +			status = "disabled";
 +		};
 +
@@ -219,6 +185,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +				 <&gcc PCIE_1_PHY_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy";
 +
++			pinctrl-0 = <&pcie1_pins>;
++			pinctrl-names = "default";
++
++			perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
++
 +			status = "disabled";
 +		};
 +
@@ -260,6 +231,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +				 <&gcc PCIE_2_PHY_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy";
 +
++			pinctrl-0 = <&pcie2_pins>;
++			pinctrl-names = "default";
++
++			perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
++
 +			status = "disabled";
 +		};
 +

target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -341,15 +341,21 @@
+@@ -369,15 +369,21 @@
  
  			clocks = <&gcc PCIE_A_CLK>,
  				 <&gcc PCIE_H_CLK>,
@@ -24,9 +24,9 @@
 +				 <&gcc PCIE_EXT_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  
- 			status = "disabled";
+ 			pinctrl-0 = <&pcie0_pins>;
- 		};
+ 			pinctrl-names = "default";
-@@ -382,15 +388,21 @@
+@@ -415,15 +421,21 @@
  
  			clocks = <&gcc PCIE_1_A_CLK>,
  				 <&gcc PCIE_1_H_CLK>,
@@ -50,9 +50,9 @@
 +				 <&gcc PCIE_1_EXT_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  
- 			status = "disabled";
+ 			pinctrl-0 = <&pcie1_pins>;
- 		};
+ 			pinctrl-names = "default";
-@@ -423,15 +435,21 @@
+@@ -461,15 +473,21 @@
  
  			clocks = <&gcc PCIE_2_A_CLK>,
  				 <&gcc PCIE_2_H_CLK>,
@@ -76,5 +76,5 @@
 +				 <&gcc PCIE_2_EXT_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  
- 			status = "disabled";
+ 			pinctrl-0 = <&pcie2_pins>;
- 		};
+ 			pinctrl-names = "default";

target/linux/ipq806x/patches-3.18/126-add-rpm-to-ipq8064-dts.patch

@@ -8,7 +8,7 @@
  #include <dt-bindings/soc/qcom,gsbi.h>
  #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
-@@ -76,6 +77,63 @@
+@@ -77,6 +78,63 @@
  		ranges;
  		compatible = "simple-bus";
  
@@ -72,7 +72,7 @@
  		qcom_pinmux: pinmux@800000 {
  			compatible = "qcom,ipq8064-pinctrl";
  			reg = <0x800000 0x4000>;
-@@ -120,6 +178,12 @@
+@@ -148,6 +206,12 @@
  			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  		};
  

target/linux/ipq806x/patches-3.18/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -24,6 +24,11 @@
+@@ -25,6 +25,11 @@
  			next-level-cache = <&L2>;
  			qcom,acc = <&acc0>;
  			qcom,saw = <&saw0>;
@@ -12,7 +12,7 @@
  		};
  
  		cpu@1 {
-@@ -34,11 +39,24 @@
+@@ -35,11 +40,24 @@
  			next-level-cache = <&L2>;
  			qcom,acc = <&acc1>;
  			qcom,saw = <&saw1>;
@@ -37,7 +37,7 @@
  		};
  	};
  
-@@ -71,6 +89,46 @@
+@@ -72,6 +90,46 @@
  		};
  	};
  
@@ -84,7 +84,7 @@
  	soc: soc {
  		#address-cells = <1>;
  		#size-cells = <1>;
-@@ -171,11 +229,13 @@
+@@ -199,11 +257,13 @@
  		acc0: clock-controller@2088000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;

target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch

@@ -13,7 +13,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -662,6 +662,26 @@
+@@ -705,6 +705,26 @@
  			};
  		};
  

target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch

@@ -26,7 +26,7 @@ arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
 
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -682,6 +682,22 @@
+@@ -725,6 +725,22 @@
  			status = "disabled";
  		};
  

target/linux/ipq806x/patches-3.18/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch

@@ -25,7 +25,7 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -61,6 +61,31 @@
+@@ -43,6 +43,31 @@
  					bias-none;
  				};
  			};
@@ -57,8 +57,8 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
  		};
  
  		gsbi@16300000 {
-@@ -149,5 +174,19 @@
+@@ -125,5 +150,19 @@
- 			pinctrl-names = "default";
+ 			status = "ok";
  			phy-tx0-term-offset = <7>;
  		};
 +

target/linux/ipq806x/patches-3.18/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -183,6 +183,8 @@
+@@ -159,6 +159,8 @@
  
  			nand-ecc-strength = <4>;
  			nand-bus-width = <8>;

target/linux/ipq806x/patches-3.18/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch

@@ -22,7 +22,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	qcom-msm8974-sony-xperia-honami.dtb
 --- /dev/null
 +++ b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
-@@ -0,0 +1,362 @@
+@@ -0,0 +1,338 @@
 +#include "qcom-ipq8064-v1.0.dtsi"
 +
 +#include <dt-bindings/input/input.h>
@@ -64,24 +64,6 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 +				bias-disable;
 +			};
 +
-+			pcie0_pins: pcie0_pinmux {
-+				mux {
-+					pins = "gpio3";
-+					function = "pcie1_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
-+			pcie1_pins: pcie1_pinmux {
-+				mux {
-+					pins = "gpio48";
-+					function = "pcie2_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
 +			nand_pins: nand_pins {
 +				mux {
 +					pins = "gpio34", "gpio35", "gpio36",
@@ -173,16 +155,10 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 +
 +		pcie0: pci@1b500000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 3 0>;
-+			pinctrl-0 = <&pcie0_pins>;
-+			pinctrl-names = "default";
 +		};
 +
 +		pcie1: pci@1b700000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 48 0>;
-+			pinctrl-0 = <&pcie1_pins>;
-+			pinctrl-names = "default";
 +		};
 +
 +		nand@1ac00000 {

target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch

@@ -22,7 +22,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  	};
  
  	chosen {
-@@ -86,6 +87,15 @@
+@@ -68,6 +69,15 @@
  					bias-bus-hold;
  				};
  			};
@@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi@16300000 {
-@@ -186,6 +196,34 @@
+@@ -162,6 +172,34 @@
  
  			linux,part-probe = "qcom-smem";
  		};
@@ -83,7 +83,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  	};
  
  	chosen {
-@@ -65,6 +66,15 @@
+@@ -38,6 +39,15 @@
  					bias-none;
  				};
  			};
@@ -99,9 +99,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi2: gsbi@12480000 {
-@@ -176,5 +186,44 @@
+@@ -140,5 +150,44 @@
- 			pinctrl-0 = <&pcie2_pins>;
+ 		pcie2: pci@1b900000 {
- 			pinctrl-names = "default";
+ 			status = "ok";
  		};
 +
 +		mdio0: mdio {

target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch

@@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -96,6 +96,16 @@
+@@ -78,6 +78,16 @@
  					bias-disable;
  				};
  			};
@@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi@16300000 {
-@@ -224,6 +234,27 @@
+@@ -200,6 +210,27 @@
  				reg = <4>;
  			};
  		};
@@ -59,7 +59,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  
 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -75,6 +75,14 @@
+@@ -48,6 +48,14 @@
  					bias-disable;
  				};
  			};
@@ -74,7 +74,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi2: gsbi@12480000 {
-@@ -225,5 +233,40 @@
+@@ -189,5 +197,40 @@
  				reg = <7>;
  			};
  		};
@@ -117,7 +117,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  };
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -698,6 +698,92 @@
+@@ -741,6 +741,92 @@
  			status = "disabled";
  		};
  

target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

@@ -15,59 +15,59 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -35,6 +35,24 @@
+@@ -91,5 +91,15 @@
- 				bias-disable;
- 			};
- 
-+			pcie0_pins: pcie0_pinmux {
-+				mux {
-+					pins = "gpio3";
-+					function = "pcie1_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
-+			pcie1_pins: pcie1_pinmux {
-+				mux {
-+					pins = "gpio48";
-+					function = "pcie2_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
- 			spi_pins: spi_pins {
- 				mux {
- 					pins = "gpio18", "gpio19", "gpio21";
-@@ -91,5 +109,21 @@
  		sata@29000000 {
  			status = "ok";
  		};
 +
 +		pcie0: pci@1b500000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 3 0>;
-+			pinctrl-0 = <&pcie0_pins>;
-+			pinctrl-names = "default";
 +			phy-tx0-term-offset = <7>;
 +		};
 +
 +		pcie1: pci@1b700000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 48 0>;
-+			pinctrl-0 = <&pcie1_pins>;
-+			pinctrl-names = "default";
 +			phy-tx0-term-offset = <7>;
 +		};
  	};
  };
 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -30,6 +30,33 @@
+@@ -128,5 +128,17 @@
- 				bias-disable;
+ 		usb30@1 {
- 			};
+ 			status = "ok";
+ 		};
++
++		pcie0: pci@1b500000 {
++			status = "ok";
++		};
++
++		pcie1: pci@1b700000 {
++			status = "ok";
++		};
++
++		pcie2: pci@1b900000 {
++			status = "ok";
++		};
+ 	};
+ };
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -4,6 +4,9 @@
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+ #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
+ #include <dt-bindings/soc/qcom,gsbi.h>
++#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/gpio/gpio.h>
  
+ / {
+ 	model = "Qualcomm IPQ8064";
+@@ -99,6 +102,33 @@
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+ 			interrupts = <0 16 0x4>;
++
 +			pcie0_pins: pcie0_pinmux {
 +				mux {
 +					pins = "gpio3";
@@ -94,49 +94,10 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +					bias-disable;
 +				};
 +			};
-+
- 			spi_pins: spi_pins {
- 				mux {
- 					pins = "gpio18", "gpio19", "gpio21";
-@@ -128,5 +155,26 @@
- 		usb30@1 {
- 			status = "ok";
  		};
-+
-+		pcie0: pci@1b500000 {
-+			status = "ok";
-+			reset-gpio = <&qcom_pinmux 3 0>;
-+			pinctrl-0 = <&pcie0_pins>;
-+			pinctrl-names = "default";
-+		};
-+
-+		pcie1: pci@1b700000 {
-+			status = "ok";
-+			reset-gpio = <&qcom_pinmux 48 0>;
-+			pinctrl-0 = <&pcie1_pins>;
-+			pinctrl-names = "default";
-+		};
-+
-+		pcie2: pci@1b900000 {
-+			status = "ok";
-+			reset-gpio = <&qcom_pinmux 63 0>;
-+			pinctrl-0 = <&pcie2_pins>;
-+			pinctrl-names = "default";
-+		};
- 	};
- };
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -4,6 +4,8 @@
- #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
- #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
- #include <dt-bindings/soc/qcom,gsbi.h>
-+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
  
- / {
+ 		intc: interrupt-controller@2000000 {
- 	model = "Qualcomm IPQ8064";
+@@ -333,6 +363,144 @@
-@@ -333,6 +335,129 @@
  			compatible = "syscon";
  			reg = <0x01200600 0x100>;
  		};
@@ -179,6 +140,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +				 <&gcc PCIE_PHY_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy";
 +
++			pinctrl-0 = <&pcie0_pins>;
++			pinctrl-names = "default";
++
++			perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
++
 +			status = "disabled";
 +		};
 +
@@ -220,6 +186,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +				 <&gcc PCIE_1_PHY_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy";
 +
++			pinctrl-0 = <&pcie1_pins>;
++			pinctrl-names = "default";
++
++			perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
++
 +			status = "disabled";
 +		};
 +
@@ -261,6 +232,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 +				 <&gcc PCIE_2_PHY_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy";
 +
++			pinctrl-0 = <&pcie2_pins>;
++			pinctrl-names = "default";
++
++			perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
++
 +			status = "disabled";
 +		};
  	};

target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -364,15 +364,21 @@
+@@ -392,15 +392,21 @@
  
  			clocks = <&gcc PCIE_A_CLK>,
  				 <&gcc PCIE_H_CLK>,
@@ -24,9 +24,9 @@
 +				 <&gcc PCIE_EXT_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  
- 			status = "disabled";
+ 			pinctrl-0 = <&pcie0_pins>;
- 		};
+ 			pinctrl-names = "default";
-@@ -405,15 +411,21 @@
+@@ -438,15 +444,21 @@
  
  			clocks = <&gcc PCIE_1_A_CLK>,
  				 <&gcc PCIE_1_H_CLK>,
@@ -50,9 +50,9 @@
 +				 <&gcc PCIE_1_EXT_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  
- 			status = "disabled";
+ 			pinctrl-0 = <&pcie1_pins>;
- 		};
+ 			pinctrl-names = "default";
-@@ -446,15 +458,21 @@
+@@ -484,15 +496,21 @@
  
  			clocks = <&gcc PCIE_2_A_CLK>,
  				 <&gcc PCIE_2_H_CLK>,
@@ -76,5 +76,5 @@
 +				 <&gcc PCIE_2_EXT_RESET>;
 +			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  
- 			status = "disabled";
+ 			pinctrl-0 = <&pcie2_pins>;
- 		};
+ 			pinctrl-names = "default";

target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch

@@ -8,7 +8,7 @@
  #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
  #include <dt-bindings/soc/qcom,gsbi.h>
  #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
-@@ -92,6 +93,63 @@
+@@ -93,6 +94,63 @@
  			reg-names = "lpass-lpaif";
  		};
  
@@ -72,7 +72,7 @@
  		qcom_pinmux: pinmux@800000 {
  			compatible = "qcom,ipq8064-pinctrl";
  			reg = <0x800000 0x4000>;
-@@ -136,6 +194,12 @@
+@@ -164,6 +222,12 @@
  			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  		};
  

target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -25,6 +25,11 @@
+@@ -26,6 +26,11 @@
  			next-level-cache = <&L2>;
  			qcom,acc = <&acc0>;
  			qcom,saw = <&saw0>;
@@ -12,7 +12,7 @@
  		};
  
  		cpu@1 {
-@@ -35,11 +40,24 @@
+@@ -36,11 +41,24 @@
  			next-level-cache = <&L2>;
  			qcom,acc = <&acc1>;
  			qcom,saw = <&saw1>;
@@ -37,7 +37,7 @@
  		};
  	};
  
-@@ -72,6 +90,46 @@
+@@ -73,6 +91,46 @@
  		};
  	};
  
@@ -84,7 +84,7 @@
  	soc: soc {
  		#address-cells = <1>;
  		#size-cells = <1>;
-@@ -187,11 +245,13 @@
+@@ -215,11 +273,13 @@
  		acc0: clock-controller@2088000 {
  			compatible = "qcom,kpss-acc-v1";
  			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;

target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch

@@ -13,7 +13,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -600,6 +600,26 @@
+@@ -643,6 +643,26 @@
  
  			status = "disabled";
  		};

target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch

@@ -26,7 +26,7 @@ arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
 
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -620,6 +620,22 @@
+@@ -663,6 +663,22 @@
  
  			status = "disabled";
  		};

target/linux/ipq806x/patches-4.1/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch

@@ -25,7 +25,7 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -61,6 +61,28 @@
+@@ -43,6 +43,28 @@
  					bias-none;
  				};
  			};
@@ -54,8 +54,8 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
  		};
  
  		gsbi@16300000 {
-@@ -125,5 +147,19 @@
+@@ -101,5 +123,19 @@
- 			pinctrl-names = "default";
+ 			status = "ok";
  			phy-tx0-term-offset = <7>;
  		};
 +

target/linux/ipq806x/patches-4.1/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -156,6 +156,8 @@
+@@ -132,6 +132,8 @@
  
  			nand-ecc-strength = <4>;
  			nand-bus-width = <8>;

target/linux/ipq806x/patches-4.1/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch

@@ -22,7 +22,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	qcom-msm8974-sony-xperia-honami.dtb
 --- /dev/null
 +++ b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
-@@ -0,0 +1,362 @@
+@@ -0,0 +1,338 @@
 +#include "qcom-ipq8064-v1.0.dtsi"
 +
 +#include <dt-bindings/input/input.h>
@@ -64,24 +64,6 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 +				bias-disable;
 +			};
 +
-+			pcie0_pins: pcie0_pinmux {
-+				mux {
-+					pins = "gpio3";
-+					function = "pcie1_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
-+			pcie1_pins: pcie1_pinmux {
-+				mux {
-+					pins = "gpio48";
-+					function = "pcie2_rst";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+			};
-+
 +			nand_pins: nand_pins {
 +				mux {
 +					pins = "gpio34", "gpio35", "gpio36",
@@ -173,16 +155,10 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 +
 +		pcie0: pci@1b500000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 3 0>;
-+			pinctrl-0 = <&pcie0_pins>;
-+			pinctrl-names = "default";
 +		};
 +
 +		pcie1: pci@1b700000 {
 +			status = "ok";
-+			reset-gpio = <&qcom_pinmux 48 0>;
-+			pinctrl-0 = <&pcie1_pins>;
-+			pinctrl-names = "default";
 +		};
 +
 +		nand@1ac00000 {

target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch

@@ -22,7 +22,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  	};
  
  	chosen {
-@@ -83,6 +84,15 @@
+@@ -65,6 +66,15 @@
  					bias-bus-hold;
  				};
  			};
@@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi@16300000 {
-@@ -159,6 +169,34 @@
+@@ -135,6 +145,34 @@
  
  			linux,part-probe = "qcom-smem";
  		};
@@ -83,7 +83,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  	};
  
  	chosen {
-@@ -65,6 +66,15 @@
+@@ -38,6 +39,15 @@
  					bias-none;
  				};
  			};
@@ -99,9 +99,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi2: gsbi@12480000 {
-@@ -176,5 +186,44 @@
+@@ -140,5 +150,44 @@
- 			pinctrl-0 = <&pcie2_pins>;
+ 		pcie2: pci@1b900000 {
- 			pinctrl-names = "default";
+ 			status = "ok";
  		};
 +
 +		mdio0: mdio {

target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch

@@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
 
 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -93,6 +93,16 @@
+@@ -75,6 +75,16 @@
  					bias-disable;
  				};
  			};
@@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi@16300000 {
-@@ -197,6 +207,27 @@
+@@ -173,6 +183,27 @@
  				reg = <4>;
  			};
  		};
@@ -59,7 +59,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  
 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -75,6 +75,14 @@
+@@ -48,6 +48,14 @@
  					bias-disable;
  				};
  			};
@@ -74,7 +74,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  		};
  
  		gsbi2: gsbi@12480000 {
-@@ -225,5 +233,40 @@
+@@ -189,5 +197,40 @@
  				reg = <7>;
  			};
  		};
@@ -117,7 +117,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  };
 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -636,6 +636,92 @@
+@@ -679,6 +679,92 @@
  
  			status = "disabled";
  		};