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@ -91,7 +91,7 @@ MODULE_PARM_DESC(debug, "debug mask (-1 for all)"); |
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/* PHY CHIP Address */ |
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/* PHY CHIP Address */ |
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#define PHY1_ADDR 1 /* For MAC1 */ |
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#define PHY1_ADDR 1 /* For MAC1 */ |
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#define PHY2_ADDR 2 /* For MAC2 */ |
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#define PHY2_ADDR 3 /* For MAC2 */ |
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#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */ |
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#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */ |
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#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */ |
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#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */ |
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@ -305,7 +305,7 @@ STATIC int phy_read(void __iomem *ioaddr, int phy_addr, int reg) |
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/* Wait for the read bit to be cleared */ |
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/* Wait for the read bit to be cleared */ |
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while (limit--) { |
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while (limit--) { |
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cmd = ioread16(ioaddr + MMDIO); |
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cmd = ioread16(ioaddr + MMDIO); |
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if (cmd & MDIO_READ) |
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if (!(cmd & MDIO_READ)) |
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break; |
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break; |
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} |
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} |
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@ -333,7 +333,7 @@ STATIC void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val) |
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/* Wait for the write bit to be cleared */ |
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/* Wait for the write bit to be cleared */ |
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while (limit--) { |
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while (limit--) { |
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cmd = ioread16(ioaddr + MMDIO); |
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cmd = ioread16(ioaddr + MMDIO); |
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if (cmd & MDIO_WRITE) |
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if (!(cmd & MDIO_WRITE)) |
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break; |
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break; |
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} |
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} |
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if (limit <= 0) |
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if (limit <= 0) |
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