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@ -152,8 +152,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> |
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+ #address-cells = <3>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #size-cells = <2>;
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+
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+
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+ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */
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+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
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+ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
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+
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+
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+ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
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+ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ interrupt-names = "msi";
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@ -193,8 +193,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> |
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+ #address-cells = <3>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #size-cells = <2>;
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+
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+
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+ ranges = <0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
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+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
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+ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
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+
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+
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+ interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
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+ interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ interrupt-names = "msi";
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@ -234,8 +234,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> |
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+ #address-cells = <3>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #size-cells = <2>;
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+
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+
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+ ranges = <0x81000000 0 0 0x35e00000 0 0x00100000 /* downstream I/O */
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+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
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+ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
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+
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+
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+ interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
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+ interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ interrupt-names = "msi";
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