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@ -120,15 +120,15 @@ enum bcm63xx_regs_set { |
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#define BCM_6358_PERF_BASE (0xfffe0000) |
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#define BCM_6358_TIMER_BASE (0xfffe0040) |
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#define BCM_6358_WDT_BASE (0xfffe005c) |
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#define BCM_6358_UART0_BASE (0xfffe0100) |
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#define BCM_6358_GPIO_BASE (0xfffe0080) |
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#define BCM_6358_SPI_BASE (0xdeadbeef) |
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#define BCM_6358_UDC0_BASE (0xfffe0800) |
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#define BCM_6358_UART0_BASE (0xfffe0100) |
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#define BCM_6358_UDC0_BASE (0xfffe0400) |
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#define BCM_6358_SPI_BASE (0xfffe0800) |
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#define BCM_6358_MPI_BASE (0xfffe1000) |
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#define BCM_6358_PCMCIA_BASE (0xfffe1054) |
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#define BCM_6358_OHCI0_BASE (0xfffe1400) |
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#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) |
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#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) |
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#define BCM_6358_MPI_BASE (0xfffe1000) |
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#define BCM_6358_PCMCIA_BASE (0xfffe1054) |
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#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) |
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#define BCM_6358_DSL_BASE (0xfffe3000) |
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#define BCM_6358_ENET0_BASE (0xfffe4000) |
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