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ar71xx: Add support for PCIe on QCA953x

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Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

SVN-Revision: 46456
master
John Crispin 9 years ago
parent 85c7f3fb29
commit 42c37d4381
2 changed files with 88 additions and 0 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 44
      target/linux/ar71xx/patches-3.18/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch
  2. 44
      target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch

44
target/linux/ar71xx/patches-3.18/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch
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@ -0,0 +1,44 @@
--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
@@ -53,6 +53,15 @@ static const struct ath79_pci_irq ar724x
}
};
+static const struct ath79_pci_irq qca953x_pci_irq_map[] __initconst = {
+ {
+ .bus = 0,
+ .slot = 0,
+ .pin = 1,
+ .irq = ATH79_PCI_IRQ(0),
+ },
+};
+
static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
{
.bus = 0,
@@ -98,6 +107,9 @@ int __init pcibios_map_irq(const struct
soc_is_ar9344()) {
ath79_pci_irq_map = ar724x_pci_irq_map;
ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
+ } else if (soc_is_qca953x()) {
+ ath79_pci_irq_map = qca953x_pci_irq_map;
+ ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map);
} else if (soc_is_qca955x()) {
ath79_pci_irq_map = qca955x_pci_irq_map;
ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
@@ -303,6 +315,15 @@ int __init ath79_register_pci(void)
AR724X_PCI_MEM_SIZE,
0,
ATH79_IP2_IRQ(0));
+ } else if (soc_is_qca9533()) {
+ pdev = ath79_register_pci_ar724x(0,
+ QCA953X_PCI_CFG_BASE0,
+ QCA953X_PCI_CTRL_BASE0,
+ QCA953X_PCI_CRP_BASE0,
+ QCA953X_PCI_MEM_BASE0,
+ QCA953X_PCI_MEM_SIZE,
+ 0,
+ ATH79_IP2_IRQ(0));
} else if (soc_is_qca9558()) {
pdev = ath79_register_pci_ar724x(0,
QCA955X_PCI_CFG_BASE0,

44
target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch
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@ -0,0 +1,44 @@
--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
@@ -53,6 +53,15 @@ static const struct ath79_pci_irq ar724x
}
};
+static const struct ath79_pci_irq qca953x_pci_irq_map[] __initconst = {
+ {
+ .bus = 0,
+ .slot = 0,
+ .pin = 1,
+ .irq = ATH79_PCI_IRQ(0),
+ },
+};
+
static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
{
.bus = 0,
@@ -98,6 +107,9 @@ int __init pcibios_map_irq(const struct
soc_is_ar9344()) {
ath79_pci_irq_map = ar724x_pci_irq_map;
ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
+ } else if (soc_is_qca953x()) {
+ ath79_pci_irq_map = qca953x_pci_irq_map;
+ ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map);
} else if (soc_is_qca955x()) {
ath79_pci_irq_map = qca955x_pci_irq_map;
ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
@@ -303,6 +315,15 @@ int __init ath79_register_pci(void)
AR724X_PCI_MEM_SIZE,
0,
ATH79_IP2_IRQ(0));
+ } else if (soc_is_qca9533()) {
+ pdev = ath79_register_pci_ar724x(0,
+ QCA953X_PCI_CFG_BASE0,
+ QCA953X_PCI_CTRL_BASE0,
+ QCA953X_PCI_CRP_BASE0,
+ QCA953X_PCI_MEM_BASE0,
+ QCA953X_PCI_MEM_SIZE,
+ 0,
+ ATH79_IP2_IRQ(0));
} else if (soc_is_qca9558()) {
pdev = ath79_register_pci_ar724x(0,
QCA955X_PCI_CFG_BASE0,
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