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@ -177,3 +177,291 @@ struct pci_ops bcm63xx_pci_ops = { |
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.read = bcm63xx_pci_read, |
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.read = bcm63xx_pci_read, |
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.write = bcm63xx_pci_write |
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.write = bcm63xx_pci_write |
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}; |
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}; |
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#ifdef CONFIG_CARDBUS |
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/*
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* emulate configuration read access on a cardbus bridge |
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*/ |
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#define FAKE_CB_BRIDGE_SLOT 0x1e |
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static int fake_cb_bridge_bus_number = -1; |
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static struct { |
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u16 pci_command; |
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u8 cb_latency; |
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u8 subordinate_busn; |
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u8 cardbus_busn; |
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u8 pci_busn; |
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int bus_assigned; |
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u16 bridge_control; |
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u32 mem_base0; |
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u32 mem_limit0; |
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u32 mem_base1; |
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u32 mem_limit1; |
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u32 io_base0; |
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u32 io_limit0; |
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u32 io_base1; |
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u32 io_limit1; |
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} fake_cb_bridge_regs; |
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static int fake_cb_bridge_read(int where, int size, u32 *val) |
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{ |
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unsigned int reg; |
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u32 data; |
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data = 0; |
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reg = where >> 2; |
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switch (reg) { |
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case (PCI_VENDOR_ID >> 2): |
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case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2): |
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/* create dummy vendor/device id from our cpu id */ |
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data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM; |
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break; |
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case (PCI_COMMAND >> 2): |
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data = (PCI_STATUS_DEVSEL_SLOW << 16); |
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data |= fake_cb_bridge_regs.pci_command; |
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break; |
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case (PCI_CLASS_REVISION >> 2): |
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data = (PCI_CLASS_BRIDGE_CARDBUS << 16); |
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break; |
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case (PCI_CACHE_LINE_SIZE >> 2): |
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data = (PCI_HEADER_TYPE_CARDBUS << 16); |
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break; |
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case (PCI_INTERRUPT_LINE >> 2): |
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/* bridge control */ |
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data = (fake_cb_bridge_regs.bridge_control << 16); |
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/* pin:intA line:0xff */ |
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data |= (0x1 << 8) | 0xff; |
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break; |
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case (PCI_CB_PRIMARY_BUS >> 2): |
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data = (fake_cb_bridge_regs.cb_latency << 24); |
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data |= (fake_cb_bridge_regs.subordinate_busn << 16); |
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data |= (fake_cb_bridge_regs.cardbus_busn << 8); |
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data |= fake_cb_bridge_regs.pci_busn; |
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break; |
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case (PCI_CB_MEMORY_BASE_0 >> 2): |
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data = fake_cb_bridge_regs.mem_base0; |
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break; |
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case (PCI_CB_MEMORY_LIMIT_0 >> 2): |
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data = fake_cb_bridge_regs.mem_limit0; |
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break; |
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case (PCI_CB_MEMORY_BASE_1 >> 2): |
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data = fake_cb_bridge_regs.mem_base1; |
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break; |
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case (PCI_CB_MEMORY_LIMIT_1 >> 2): |
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data = fake_cb_bridge_regs.mem_limit1; |
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break; |
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case (PCI_CB_IO_BASE_0 >> 2): |
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/* | 1 for 32bits io support */ |
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data = fake_cb_bridge_regs.io_base0 | 0x1; |
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break; |
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case (PCI_CB_IO_LIMIT_0 >> 2): |
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data = fake_cb_bridge_regs.io_limit0; |
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break; |
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case (PCI_CB_IO_BASE_1 >> 2): |
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/* | 1 for 32bits io support */ |
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data = fake_cb_bridge_regs.io_base1 | 0x1; |
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break; |
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case (PCI_CB_IO_LIMIT_1 >> 2): |
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data = fake_cb_bridge_regs.io_limit1; |
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break; |
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} |
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*val = postprocess_read(data, where, size); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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/*
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* emulate configuration write access on a cardbus bridge |
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*/ |
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static int fake_cb_bridge_write(int where, int size, u32 val) |
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{ |
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unsigned int reg; |
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u32 data, tmp; |
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int ret; |
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ret = fake_cb_bridge_read((where & ~0x3), 4, &data); |
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if (ret != PCIBIOS_SUCCESSFUL) |
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return ret; |
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data = preprocess_write(data, val, where, size); |
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reg = where >> 2; |
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switch (reg) { |
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case (PCI_COMMAND >> 2): |
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fake_cb_bridge_regs.pci_command = (data & 0xffff); |
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break; |
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case (PCI_CB_PRIMARY_BUS >> 2): |
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fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff; |
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fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff; |
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fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff; |
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fake_cb_bridge_regs.pci_busn = data & 0xff; |
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if (fake_cb_bridge_regs.cardbus_busn) |
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fake_cb_bridge_regs.bus_assigned = 1; |
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break; |
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case (PCI_INTERRUPT_LINE >> 2): |
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tmp = (data >> 16) & 0xffff; |
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/* disable memory prefetch support */ |
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tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
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tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; |
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fake_cb_bridge_regs.bridge_control = tmp; |
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break; |
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case (PCI_CB_MEMORY_BASE_0 >> 2): |
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fake_cb_bridge_regs.mem_base0 = data; |
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break; |
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case (PCI_CB_MEMORY_LIMIT_0 >> 2): |
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fake_cb_bridge_regs.mem_limit0 = data; |
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break; |
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case (PCI_CB_MEMORY_BASE_1 >> 2): |
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fake_cb_bridge_regs.mem_base1 = data; |
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break; |
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case (PCI_CB_MEMORY_LIMIT_1 >> 2): |
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fake_cb_bridge_regs.mem_limit1 = data; |
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break; |
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case (PCI_CB_IO_BASE_0 >> 2): |
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fake_cb_bridge_regs.io_base0 = data; |
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break; |
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case (PCI_CB_IO_LIMIT_0 >> 2): |
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fake_cb_bridge_regs.io_limit0 = data; |
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break; |
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case (PCI_CB_IO_BASE_1 >> 2): |
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fake_cb_bridge_regs.io_base1 = data; |
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break; |
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case (PCI_CB_IO_LIMIT_1 >> 2): |
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fake_cb_bridge_regs.io_limit1 = data; |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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/* snoop access to slot 0x1e on root bus, we fake a cardbus
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* bridge at this location */ |
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if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) { |
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fake_cb_bridge_bus_number = bus->number; |
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return fake_cb_bridge_read(where, size, val); |
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} |
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/* a configuration cycle for the device behind the cardbus
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* bridge is actually done as a type 0 cycle on the primary |
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* bus. This means that only one device can be on the cardbus |
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* bus */ |
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if (fake_cb_bridge_regs.bus_assigned && |
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bus->number == fake_cb_bridge_regs.cardbus_busn && |
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PCI_SLOT(devfn) == 0) |
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return bcm63xx_do_cfg_read(0, 0, |
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PCI_DEVFN(CARDBUS_PCI_IDSEL, 0), |
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where, size, val); |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) { |
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fake_cb_bridge_bus_number = bus->number; |
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return fake_cb_bridge_write(where, size, val); |
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} |
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if (fake_cb_bridge_regs.bus_assigned && |
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bus->number == fake_cb_bridge_regs.cardbus_busn && |
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PCI_SLOT(devfn) == 0) |
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return bcm63xx_do_cfg_write(0, 0, |
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PCI_DEVFN(CARDBUS_PCI_IDSEL, 0), |
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where, size, val); |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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struct pci_ops bcm63xx_cb_ops = { |
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.read = bcm63xx_cb_read, |
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.write = bcm63xx_cb_write, |
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}; |
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/*
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* only one IO window, so it cannot be shared by PCI and cardbus, use |
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* fixup to choose and detect unhandled configuration |
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*/ |
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static void bcm63xx_fixup(struct pci_dev *dev) |
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{ |
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static int io_window = -1; |
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int i, found, new_io_window; |
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u32 val; |
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/* look for any io resource */ |
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found = 0; |
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
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if (pci_resource_flags(dev, i) & IORESOURCE_IO) { |
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found = 1; |
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break; |
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} |
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} |
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if (!found) |
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return; |
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|
|
/* skip our fake bus with only cardbus bridge on it */ |
|
|
|
|
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|
|
if (dev->bus->number == fake_cb_bridge_bus_number) |
|
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|
|
return; |
|
|
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|
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|
|
|
|
|
|
|
/* find on which bus the device is */ |
|
|
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|
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|
|
if (fake_cb_bridge_regs.bus_assigned && |
|
|
|
|
|
|
|
dev->bus->number == fake_cb_bridge_regs.cardbus_busn && |
|
|
|
|
|
|
|
PCI_SLOT(dev->devfn) == 0) |
|
|
|
|
|
|
|
new_io_window = 1; |
|
|
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|
|
else |
|
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|
|
new_io_window = 0; |
|
|
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|
|
|
|
|
|
|
|
|
|
|
if (new_io_window == io_window) |
|
|
|
|
|
|
|
return; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (io_window != -1) { |
|
|
|
|
|
|
|
printk(KERN_ERR "bcm63xx: both PCI and cardbus devices " |
|
|
|
|
|
|
|
"need IO, which hardware cannot do\n"); |
|
|
|
|
|
|
|
return; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n", |
|
|
|
|
|
|
|
(new_io_window == 0) ? "PCI" : "cardbus"); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val = bcm_mpi_readl(MPI_L2PIOREMAP_REG); |
|
|
|
|
|
|
|
if (io_window) |
|
|
|
|
|
|
|
val |= MPI_L2PREMAP_IS_CARDBUS_MASK; |
|
|
|
|
|
|
|
else |
|
|
|
|
|
|
|
val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK; |
|
|
|
|
|
|
|
bcm_mpi_writel(val, MPI_L2PIOREMAP_REG); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
io_window = new_io_window; |
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup); |
|
|
|
|
|
|
|
#endif |
|
|
|