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@ -1,3 +1,21 @@ |
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commit b14fbb554fc65a2e0b5c41a319269b0350f187e7
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Author: Felix Fietkau <nbd@openwrt.org>
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Date: Sat Feb 22 14:35:25 2014 +0100
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ath9k: do not set half/quarter channel flags in AR_PHY_MODE
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5/10 MHz channel bandwidth is configured via the PLL clock, instead of
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the AR_PHY_MODE register. Using that register is AR93xx specific, and
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makes the mode incompatible with earlier chipsets.
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In some early versions, these flags were apparently applied at the wrong
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point in time and thus did not cause connectivity issues, however now
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they are causing problems, as pointed out in this OpenWrt ticket:
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https://dev.openwrt.org/ticket/14916
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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commit 0f1cb7be2551b30b02cd54c897e0e29e483cfda5
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Author: Felix Fietkau <nbd@openwrt.org>
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Date: Sat Feb 22 13:43:29 2014 +0100
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@ -3296,3 +3314,16 @@ Date: Thu Jan 23 20:06:34 2014 +0100 |
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"%17s: %2d\n", "MCI Reset",
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sc->debug.stats.reset[RESET_TYPE_MCI]);
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--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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@@ -868,10 +868,6 @@ static void ar9003_hw_set_rfmode(struct
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if (IS_CHAN_A_FAST_CLOCK(ah, chan))
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rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
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- if (IS_CHAN_QUARTER_RATE(chan))
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- rfMode |= AR_PHY_MODE_QUARTER;
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- if (IS_CHAN_HALF_RATE(chan))
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- rfMode |= AR_PHY_MODE_HALF;
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if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
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REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
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