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@ -31,14 +31,15 @@ |
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#define PACE_OFFSET 0xA0 |
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#define PACE_OFFSET 0xA0 |
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#define CHNLS_OFFSET 0x200 |
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#define CHNLS_OFFSET 0x200 |
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#define IRQ_NUM(irq) (irq % 40 % 32) |
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#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) |
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#define REG_OFFSET(irq, reg) (((irq) < 40) ? \ |
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#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8) |
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((irq) / 32 * 0x4 + reg * 0x10) : \
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#define SR_OFFSET (SEC_REG_OFFSET(0)) |
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(EXCEPT_OFFSET + reg * 0x8))
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#define SR_OFFSET(irq) (REG_OFFSET(irq, 0)) |
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#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) |
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#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) |
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#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) |
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#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) |
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#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) |
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#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) |
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#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) |
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#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) |
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#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) |
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#define PIR_OFFSET (0x40) |
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#define PIR_OFFSET (0x40) |
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#define MSR_OFFSET (0x44) |
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#define MSR_OFFSET (0x44) |
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#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) |
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#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) |
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@ -50,8 +51,12 @@ |
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static void ar7_unmask_irq(unsigned int irq_nr); |
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static void ar7_unmask_irq(unsigned int irq_nr); |
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static void ar7_mask_irq(unsigned int irq_nr); |
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static void ar7_mask_irq(unsigned int irq_nr); |
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static void ar7_unmask_secondary_irq(unsigned int irq_nr); |
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static void ar7_mask_secondary_irq(unsigned int irq_nr); |
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static irqreturn_t ar7_cascade(int interrupt, void *dev); |
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static irqreturn_t ar7_cascade(int interrupt, void *dev); |
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void ar7_irq_init(int); |
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static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev); |
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static void ar7_irq_init(int base); |
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static int ar7_irq_base; |
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static struct irq_chip ar7_irq_type = { |
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static struct irq_chip ar7_irq_type = { |
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.name = "AR7", |
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.name = "AR7", |
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@ -59,20 +64,28 @@ static struct irq_chip ar7_irq_type = { |
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.mask = ar7_mask_irq, |
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.mask = ar7_mask_irq, |
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}; |
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}; |
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static int ar7_irq_base; |
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static struct irq_chip ar7_secondary_irq_type = { |
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.name = "AR7", |
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.unmask = ar7_unmask_secondary_irq, |
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.mask = ar7_mask_secondary_irq, |
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}; |
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static struct irqaction ar7_cascade_action = { |
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static struct irqaction ar7_cascade_action = { |
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.handler = ar7_cascade,
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.handler = ar7_cascade,
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.name = "AR7 cascade interrupt" |
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.name = "AR7 cascade interrupt" |
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}; |
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}; |
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static struct irqaction ar7_secondary_cascade_action = { |
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.handler = ar7_secondary_cascade,
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.name = "AR7 secondary cascade interrupt" |
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}; |
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static void ar7_unmask_irq(unsigned int irq) |
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static void ar7_unmask_irq(unsigned int irq) |
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{ |
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{ |
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unsigned long flags; |
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unsigned long flags; |
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local_irq_save(flags); |
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local_irq_save(flags); |
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/* enable the interrupt channel bit */ |
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/* enable the interrupt channel bit */ |
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REG(ESR_OFFSET(irq - ar7_irq_base)) = 1 << IRQ_NUM(irq - ar7_irq_base); |
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REG(ESR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32); |
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local_irq_restore(flags); |
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local_irq_restore(flags); |
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} |
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} |
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@ -81,7 +94,25 @@ static void ar7_mask_irq(unsigned int irq) |
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unsigned long flags; |
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unsigned long flags; |
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local_irq_save(flags); |
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local_irq_save(flags); |
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/* disable the interrupt channel bit */ |
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/* disable the interrupt channel bit */ |
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REG(ECR_OFFSET(irq - ar7_irq_base)) = 1 << IRQ_NUM(irq - ar7_irq_base); |
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REG(ECR_OFFSET(irq)) = 1 << ((irq - ar7_irq_base) % 32); |
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local_irq_restore(flags); |
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} |
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static void ar7_unmask_secondary_irq(unsigned int irq) |
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{ |
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unsigned long flags; |
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local_irq_save(flags); |
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/* enable the interrupt channel bit */ |
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REG(SEC_ESR_OFFSET) = 1 << (irq - ar7_irq_base - 40); |
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local_irq_restore(flags); |
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} |
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static void ar7_mask_secondary_irq(unsigned int irq) |
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{ |
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unsigned long flags; |
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local_irq_save(flags); |
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/* disable the interrupt channel bit */ |
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REG(SEC_ECR_OFFSET) = 1 << (irq - ar7_irq_base - 40); |
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local_irq_restore(flags); |
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local_irq_restore(flags); |
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} |
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} |
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@ -90,7 +121,7 @@ void __init arch_init_irq(void) { |
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ar7_irq_init(8); |
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ar7_irq_init(8); |
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} |
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} |
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void __init ar7_irq_init(int base) |
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static void __init ar7_irq_init(int base) |
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{ |
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{ |
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int i; |
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int i; |
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/*
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/*
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@ -98,54 +129,67 @@ void __init ar7_irq_init(int base) |
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*/ |
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*/ |
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REG(ECR_OFFSET(0)) = 0xffffffff; |
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REG(ECR_OFFSET(0)) = 0xffffffff; |
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REG(ECR_OFFSET(32)) = 0xff; |
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REG(ECR_OFFSET(32)) = 0xff; |
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REG(ECR_OFFSET(40)) = 0xffffffff; |
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REG(SEC_ECR_OFFSET) = 0xffffffff; |
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REG(CR_OFFSET(0)) = 0xffffffff; |
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REG(CR_OFFSET(0)) = 0xffffffff; |
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REG(CR_OFFSET(32)) = 0xff; |
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REG(CR_OFFSET(32)) = 0xff; |
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REG(CR_OFFSET(40)) = 0xffffffff; |
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REG(SEC_CR_OFFSET) = 0xffffffff; |
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ar7_irq_base = base; |
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for(i = 0; i < 40; i++) { |
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for(i = 0; i < 40; i++) { |
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REG(CHNL_OFFSET(i)) = i; |
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REG(CHNL_OFFSET(i)) = i; |
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/* Primary IRQ's */ |
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/* Primary IRQ's */ |
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irq_desc[i + base].status = IRQ_DISABLED; |
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irq_desc[i + base].status = IRQ_DISABLED; |
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irq_desc[i + base].action = 0; |
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irq_desc[i + base].action = NULL; |
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irq_desc[i + base].depth = 1; |
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irq_desc[i + base].depth = 1; |
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irq_desc[i + base].chip = &ar7_irq_type; |
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irq_desc[i + base].chip = &ar7_irq_type; |
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/* Secondary IRQ's */ |
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/* Secondary IRQ's */ |
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if (i < 32) { |
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if (i < 32) { |
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irq_desc[i + base + 40].status = IRQ_DISABLED; |
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irq_desc[i + base + 40].status = IRQ_DISABLED; |
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irq_desc[i + base + 40].action = 0; |
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irq_desc[i + base + 40].action = NULL; |
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irq_desc[i + base + 40].depth = 1; |
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irq_desc[i + base + 40].depth = 1; |
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irq_desc[i + base + 40].chip = |
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irq_desc[i + base + 40].chip = &ar7_secondary_irq_type; |
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&ar7_irq_type; |
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} |
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} |
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} |
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} |
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ar7_irq_base = base; |
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setup_irq(2, &ar7_cascade_action); |
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setup_irq(2, &ar7_cascade_action); |
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setup_irq(ar7_irq_base, &ar7_secondary_cascade_action); |
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set_c0_status(IE_IRQ0); |
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set_c0_status(IE_IRQ0); |
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} |
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} |
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static irqreturn_t ar7_cascade(int interrupt, void *dev) |
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static irqreturn_t ar7_cascade(int interrupt, void *dev) |
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{ |
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{ |
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int irq, i; |
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int irq; |
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unsigned long status; |
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irq = (REG(PIR_OFFSET) & 0x3F); |
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irq = (REG(PIR_OFFSET) & 0x3F); |
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if (irq == 40) return IRQ_NONE; |
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REG(CR_OFFSET(irq)) = 1 << (irq % 32); |
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if (irq > 0) { |
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REG(CR_OFFSET(irq)) = 1 << IRQ_NUM(irq); |
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do_IRQ(irq + ar7_irq_base); |
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} else { |
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status = REG(SR_OFFSET(40)); |
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return IRQ_HANDLED; |
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for (i = 0; i < 32; i++) { |
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} |
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if (status & (i << 1)) { |
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irq = i + 40; |
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static irqreturn_t ar7_secondary_cascade(int interrupt, void *dev) |
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REG(CR_OFFSET(irq)) = 1 << i; |
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{ |
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break; |
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int irq = 0, i; |
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} |
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unsigned long status; |
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} |
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REG(CR_OFFSET(0)) = 1; |
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status = REG(SR_OFFSET); |
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if (unlikely(!status)) { |
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spurious_interrupt(); |
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return IRQ_NONE; |
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} |
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} |
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return do_IRQ(irq + ar7_irq_base); |
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for (i = 0; i < 32; i++) |
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if (status & (i << 1)) { |
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irq = i + 40; |
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REG(SEC_CR_OFFSET) = 1 << i; |
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break; |
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} |
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do_IRQ(irq + ar7_irq_base); |
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return IRQ_HANDLED; |
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} |
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} |
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asmlinkage void plat_irq_dispatch(void) |
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asmlinkage void plat_irq_dispatch(void) |
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