(used if the boot loader wants a different loadaddr/entry) Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 44014master
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#
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# Makefile for the LZMA compressed kernel loader for
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# Atheros AR7XXX/AR9XXX based boards
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#
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# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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#
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# Some parts of this file was based on the OpenWrt specific lzma-loader
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# for the BCM47xx and ADM5120 based boards:
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# Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
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# Copyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>
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# Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License version 2 as published
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# by the Free Software Foundation.
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#
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LOADADDR :=
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LZMA_TEXT_START := 0x81000000
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LOADER_DATA :=
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BOARD :=
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FLASH_OFFS :=
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FLASH_MAX :=
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PLATFORM :=
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CC := $(CROSS_COMPILE)gcc
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LD := $(CROSS_COMPILE)ld
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OBJCOPY := $(CROSS_COMPILE)objcopy
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OBJDUMP := $(CROSS_COMPILE)objdump
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BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
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CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
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-fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \
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-mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \
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-fno-common -ffreestanding -fhonour-copts \
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-mabi=32 -march=mips32r2 \
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-Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap \
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-DCONFIG_CACHELINE_SIZE=32 -DKERNEL_ADDR=$(KERNEL_ADDR)
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ASFLAGS = $(CFLAGS) -D__ASSEMBLY__
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LDFLAGS = -static --gc-sections -no-warn-mismatch
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LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START)
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O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
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OBJECTS := head.o
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all: head.o loader.bin |
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# Don't build dependencies, this may die if $(CC) isn't gcc
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dep: |
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install: |
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%.o : %.c |
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$(CC) $(CFLAGS) -c -o $@ $<
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%.o : %.S |
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$(CC) $(ASFLAGS) -c -o $@ $<
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loader: $(OBJECTS) |
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$(LD) $(LDFLAGS) -o $@ $(OBJECTS)
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loader.bin: loader |
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$(OBJCOPY) $(BIN_FLAGS) $< $@
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mrproper: clean |
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clean: |
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rm -f loader *.elf *.bin *.o
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@ -0,0 +1,85 @@ |
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/*
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* Cache operations for the cache instruction. |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle |
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* (C) Copyright 1999 Silicon Graphics, Inc. |
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*/ |
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#ifndef __ASM_CACHEOPS_H |
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#define __ASM_CACHEOPS_H |
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/*
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* Cache Operations available on all MIPS processors with R4000-style caches |
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*/ |
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#define Index_Invalidate_I 0x00 |
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#define Index_Writeback_Inv_D 0x01 |
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#define Index_Load_Tag_I 0x04 |
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#define Index_Load_Tag_D 0x05 |
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#define Index_Store_Tag_I 0x08 |
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#define Index_Store_Tag_D 0x09 |
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#if defined(CONFIG_CPU_LOONGSON2) |
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#define Hit_Invalidate_I 0x00 |
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#else |
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#define Hit_Invalidate_I 0x10 |
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#endif |
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#define Hit_Invalidate_D 0x11 |
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#define Hit_Writeback_Inv_D 0x15 |
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/*
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* R4000-specific cacheops |
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*/ |
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#define Create_Dirty_Excl_D 0x0d |
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#define Fill 0x14 |
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#define Hit_Writeback_I 0x18 |
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#define Hit_Writeback_D 0x19 |
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/*
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* R4000SC and R4400SC-specific cacheops |
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*/ |
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#define Index_Invalidate_SI 0x02 |
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#define Index_Writeback_Inv_SD 0x03 |
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#define Index_Load_Tag_SI 0x06 |
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#define Index_Load_Tag_SD 0x07 |
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#define Index_Store_Tag_SI 0x0A |
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#define Index_Store_Tag_SD 0x0B |
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#define Create_Dirty_Excl_SD 0x0f |
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#define Hit_Invalidate_SI 0x12 |
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#define Hit_Invalidate_SD 0x13 |
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#define Hit_Writeback_Inv_SD 0x17 |
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#define Hit_Writeback_SD 0x1b |
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#define Hit_Set_Virtual_SI 0x1e |
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#define Hit_Set_Virtual_SD 0x1f |
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/*
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* R5000-specific cacheops |
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*/ |
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#define R5K_Page_Invalidate_S 0x17 |
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/*
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* RM7000-specific cacheops |
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*/ |
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#define Page_Invalidate_T 0x16 |
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/*
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* R10000-specific cacheops |
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* |
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* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. |
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* Most of the _S cacheops are identical to the R4000SC _SD cacheops. |
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*/ |
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#define Index_Writeback_Inv_S 0x03 |
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#define Index_Load_Tag_S 0x07 |
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#define Index_Store_Tag_S 0x0B |
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#define Hit_Invalidate_S 0x13 |
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#define Cache_Barrier 0x14 |
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#define Hit_Writeback_Inv_S 0x17 |
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#define Index_Load_Data_I 0x18 |
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#define Index_Load_Data_D 0x19 |
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#define Index_Load_Data_S 0x1b |
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#define Index_Store_Data_I 0x1c |
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#define Index_Store_Data_D 0x1d |
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#define Index_Store_Data_S 0x1f |
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#endif /* __ASM_CACHEOPS_H */ |
@ -0,0 +1,39 @@ |
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/*
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* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle |
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* |
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* Copyright (C) 2001, Monta Vista Software |
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* Author: jsun@mvista.com or jsun@junsun.net |
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*/ |
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#ifndef _cp0regdef_h_ |
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#define _cp0regdef_h_ |
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#define CP0_INDEX $0 |
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#define CP0_RANDOM $1 |
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#define CP0_ENTRYLO0 $2 |
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#define CP0_ENTRYLO1 $3 |
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#define CP0_CONTEXT $4 |
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#define CP0_PAGEMASK $5 |
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#define CP0_WIRED $6 |
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#define CP0_BADVADDR $8 |
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#define CP0_COUNT $9 |
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#define CP0_ENTRYHI $10 |
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#define CP0_COMPARE $11 |
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#define CP0_STATUS $12 |
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#define CP0_CAUSE $13 |
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#define CP0_EPC $14 |
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#define CP0_PRID $15 |
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#define CP0_CONFIG $16 |
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#define CP0_LLADDR $17 |
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#define CP0_WATCHLO $18 |
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#define CP0_WATCHHI $19 |
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#define CP0_XCONTEXT $20 |
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#define CP0_FRAMEMASK $21 |
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#define CP0_DIAGNOSTIC $22 |
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#define CP0_PERFORMANCE $25 |
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#define CP0_ECC $26 |
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#define CP0_CACHEERR $27 |
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#define CP0_TAGLO $28 |
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#define CP0_TAGHI $29 |
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#define CP0_ERROREPC $30 |
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#endif |
@ -0,0 +1,153 @@ |
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/* |
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* LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards |
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* |
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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* |
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* Some parts of this code was based on the OpenWrt specific lzma-loader |
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* for the BCM47xx and ADM5120 based boards: |
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* Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
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* Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
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* |
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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*/ |
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#include <asm/asm.h> |
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#include <asm/regdef.h> |
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#include "cp0regdef.h" |
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#include "cacheops.h" |
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#define KSEG0 0x80000000 |
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.macro ehb
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sll zero, 3 |
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.endm |
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.macro reset
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li t0, 0xbe000034 |
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lw t1, 0(t0) |
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ori t1, 1 |
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sw t1, 0(t0) |
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.endm |
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.text |
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LEAF(startup) |
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.set noreorder
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.set mips32
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.fill 0x10000
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mtc0 zero, CP0_WATCHLO # clear watch registers |
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mtc0 zero, CP0_WATCHHI |
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mtc0 zero, CP0_CAUSE # clear before writing status register |
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mfc0 t0, CP0_STATUS |
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li t1, 0x1000001f |
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or t0, t1 |
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xori t0, 0x1f |
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mtc0 t0, CP0_STATUS |
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ehb |
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mtc0 zero, CP0_COUNT |
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mtc0 zero, CP0_COMPARE |
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ehb |
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la t0, __reloc_label # get linked address of label |
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bal __reloc_label # branch and link to label to |
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nop # get actual address |
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__reloc_label: |
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subu t0, ra, t0 # get reloc_delta |
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/* Copy our code to the right place */ |
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la t1, _code_start # get linked address of _code_start |
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la t2, _code_end # get linked address of _code_end |
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addu t4, t2, t0 # calculate actual address of _code_end |
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lw t5, 0(t4) # get extra data size |
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add t2, t5 |
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add t2, 4 |
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add t0, t1 # calculate actual address of _code_start |
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__reloc_copy: |
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lw t3, 0(t0) |
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sw t3, 0(t1) |
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add t1, 4 |
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blt t1, t2, __reloc_copy |
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add t0, 4 |
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/* flush cache */ |
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la t0, _code_start |
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la t1, _code_end |
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li t2, ~(CONFIG_CACHELINE_SIZE - 1) |
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and t0, t2 |
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and t1, t2 |
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li t2, CONFIG_CACHELINE_SIZE |
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b __flush_check |
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nop |
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__flush_line: |
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cache Hit_Writeback_Inv_D, 0(t0) |
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cache Hit_Invalidate_I, 0(t0) |
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add t0, t2 |
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__flush_check: |
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bne t0, t1, __flush_line |
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nop |
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sync |
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la t0, __reloc_back |
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j t0 |
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nop |
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__reloc_back: |
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la t0, _code_end |
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add t0, 4 |
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addu t1, t0, t5 |
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li t2, KERNEL_ADDR |
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__kernel_copy: |
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lw t3, 0(t0) |
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sw t3, 0(t2) |
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add t0, 4 |
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blt t0, t1, __kernel_copy |
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add t2, 4 |
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/* flush cache */ |
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li t0, KERNEL_ADDR |
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addu t1, t0, t5 |
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add t1, CONFIG_CACHELINE_SIZE - 1 |
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li t2, ~(CONFIG_CACHELINE_SIZE - 1) |
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and t0, t2 |
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and t1, t2 |
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li t2, CONFIG_CACHELINE_SIZE |
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b __kernel_flush_check |
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nop |
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__kernel_flush_line: |
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cache Hit_Writeback_Inv_D, 0(t0) |
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cache Hit_Invalidate_I, 0(t0) |
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add t0, t2 |
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__kernel_flush_check: |
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bne t0, t1, __kernel_flush_line |
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nop |
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sync |
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li t0, KERNEL_ADDR |
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jr t0 |
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nop |
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.set reorder
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END(startup) |
@ -0,0 +1,16 @@ |
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OUTPUT_ARCH(mips) |
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SECTIONS { |
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.text : { |
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_code_start = .; |
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*(.text) |
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*(.text.*) |
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*(.rodata) |
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*(.rodata.*) |
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*(.data) |
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*(.data.*) |
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} |
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. = ALIGN(32); |
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_code_end = .; |
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} |
Loading…
Reference in new issue