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ar71xx: use the ath79_set_ar934x_eth_cfg helper in machine setup routines

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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 33818
master
Gabor Juhos 12 years ago
parent 5ffc08e3dc
commit 31387947c8
5 changed files with 7 additions and 97 deletions
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  1. 23
      target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c
  2. 20
      target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
  3. 19
      target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c
  4. 20
      target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c
  5. 22
      target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c

23
target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c
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@ -175,27 +175,6 @@ static void __init om2p_lc_setup(void)
MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup);
static void __init om2p_hs_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
t |= AR934X_ETH_CFG_SW_PHY_SWAP;
__raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init om2p_hs_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
@ -222,7 +201,7 @@ static void __init om2p_hs_setup(void)
ath79_register_wmac(art, NULL);
om2p_hs_gmac_setup();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);

20
target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c
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@ -123,23 +123,6 @@ static struct mdio_board_info rb2011_mdio0_info[] = {
},
};
static void __init rb2011_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
__raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init rb2011_wlan_init(void)
{
u8 *hard_cfg = (u8 *) KSEG1ADDR(0x1f000000 + RB_HARD_CFG_OFFSET);
@ -232,7 +215,8 @@ static void __init rb2011_setup(void)
ath79_register_m25p80(&rb2011_spi_flash_data);
rb2011_nand_init();
rb2011_gmac_setup();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);

19
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c
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@ -139,23 +139,6 @@ static struct mdio_board_info wdr4300_mdio0_info[] = {
},
};
static void __init wdr4300_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
t |= AR934X_ETH_CFG_RGMII_GMAC0;
__raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init wdr4300_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@ -176,7 +159,7 @@ static void __init wdr4300_setup(void)
ap9x_pci_setup_wmac_led_pin(0, 0);
ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
wdr4300_gmac_setup();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wdr4300_mdio0_info,
ARRAY_SIZE(wdr4300_mdio0_info));

20
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c
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@ -101,23 +101,6 @@ static struct mdio_board_info db120_mdio0_info[] = {
},
};
static void __init db120_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
__raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init tl_wr1041nv2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@ -132,7 +115,8 @@ static void __init tl_wr1041nv2_setup(void)
tl_wr1041nv2_gpio_keys);
ath79_register_wmac(ee, mac);
db120_gmac_setup();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);

22
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c
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@ -99,26 +99,6 @@ static struct gpio_keys_button tl_wr841n_v8_gpio_keys[] __initdata = {
}
};
static void __init tl_wr841n_v8_gmac_setup(void)
{
void __iomem *base;
u32 t;
base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
t |= AR934X_ETH_CFG_SW_PHY_SWAP;
__raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init tl_wr841n_v8_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
@ -133,7 +113,7 @@ static void __init tl_wr841n_v8_setup(void)
ath79_register_m25p80(&tl_wr841n_v8_flash_data);
tl_wr841n_v8_gmac_setup();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);

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