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@ -871,7 +871,8 @@ for (i = 0; i < RX_DCNT; i++) { |
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if (PHY_MODE == 0x3100) |
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lp->phy_mode = phy_mode_chk(dev); |
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else lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0; |
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else |
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lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0; |
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} |
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/* MAC Bus Control Register */ |
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outw(MBCR_DEFAULT, ioaddr+0x8); |
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@ -880,6 +881,16 @@ for (i = 0; i < RX_DCNT; i++) { |
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lp->mcr0 |= lp->phy_mode; |
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outw(lp->mcr0, ioaddr); |
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/* set interrupt waiting time and packet numbers */ |
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outw(0x0802, ioaddr + 0x0C); |
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outw(0x0802, ioaddr + 0x10); |
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/* upgrade performance (by RDC guys) */ |
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phy_write(ioaddr,30,17,(phy_read(ioaddr,30,17)|0x4000)); //bit 14=1
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phy_write(ioaddr,30,17,~((~phy_read(ioaddr,30,17))|0x2000)); //bit 13=0
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phy_write(ioaddr,0,19,0x0000); |
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phy_write(ioaddr,0,30,0x01F0); |
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/* Interrupt Mask Register */ |
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outw(R6040_INT_MASK, ioaddr + 0x40); |
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} |
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