ar71xx: also use the ath79_set_ar934x_eth_cfg helper for DB120

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 33819

target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch

@@ -63,7 +63,7 @@
  };
  
  static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-@@ -76,66 +93,101 @@ static struct gpio_keys_button db120_gpi
+@@ -76,66 +93,85 @@ static struct gpio_keys_button db120_gpi
  	},
  };
  
@@ -111,47 +111,36 @@
  
 -#ifdef CONFIG_PCI
 -static struct ath9k_platform_data db120_ath9k_data;
-+static struct mdio_board_info db120_mdio0_info[] = {
-+	{
-+		.bus_id = "ag71xx-mdio.0",
-+		.phy_addr = 0,
-+		.platform_data = &db120_ar8327_data,
-+	},
-+};
- 
+-
 -static int db120_pci_plat_dev_init(struct pci_dev *dev)
-+static void __init db120_gmac_setup(void)
- {
+-{
 -	switch (PCI_SLOT(dev->devfn)) {
 -	case 0:
 -		dev->dev.platform_data = &db120_ath9k_data;
 -		break;
 -	}
-+	void __iomem *base;
-+	u32 t;
- 
+-
 -	return 0;
 -}
-+	base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
- 
+-
 -static void __init db120_pci_init(u8 *eeprom)
 -{
 -	memcpy(db120_ath9k_data.eeprom_data, eeprom,
 -	       sizeof(db120_ath9k_data.eeprom_data));
-+	t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-+	t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-+	       AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-+	t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
-+
-+	__raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
- 
+-
 -	ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
 -	ath79_register_pci();
-+	iounmap(base);
- }
+-}
 -#else
 -static inline void db120_pci_init(void) {}
 -#endif /* CONFIG_PCI */
++static struct mdio_board_info db120_mdio0_info[] = {
++	{
++		.bus_id = "ag71xx-mdio.0",
++		.phy_addr = 0,
++		.platform_data = &db120_ar8327_data,
++	},
++};
  
  static void __init db120_setup(void)
  {
@@ -172,7 +161,8 @@
 -	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
 +	ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
 +
-+	db120_gmac_setup();
++	ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
++				   AR934X_ETH_CFG_SW_ONLY_MODE);
 +
 +	ath79_register_mdio(1, 0x0);
 +	ath79_register_mdio(0, 0x0);