parent
d085aad288
commit
1bd8db0bd6
@ -1,35 +0,0 @@ |
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -4,6 +4,7 @@
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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@@ -22,6 +23,14 @@ static inline u32 bcma_cc_write32_masked
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return value;
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}
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+static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
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+{
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+ if (cc->capabilities & BCMA_CC_CAP_PMU)
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+ return bcma_pmu_alp_clock(cc);
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+
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+ return 20000000;
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+}
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+
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void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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{
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if (cc->early_setup_done)
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@@ -180,8 +189,7 @@ void bcma_chipco_serial_init(struct bcma
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struct bcma_serial_port *ports = cc->serial_ports;
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if (ccrev >= 11 && ccrev != 15) {
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- /* Fixed ALP clock */
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- baud_base = bcma_pmu_alp_clock(cc);
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+ baud_base = bcma_chipco_alp_clock(cc);
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if (ccrev >= 21) {
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/* Turn off UART clock before switching clocksource. */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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@ -1,57 +0,0 @@ |
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -31,6 +31,28 @@ static u32 bcma_chipco_alp_clock(struct
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return 20000000;
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}
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+static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+ u32 nb;
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+
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+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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+ nb = 32;
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+ else if (cc->core->id.rev < 26)
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+ nb = 16;
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+ else
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+ nb = (cc->core->id.rev >= 37) ? 32 : 24;
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+ } else {
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+ nb = 28;
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+ }
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+ if (nb == 32)
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+ return 0xffffffff;
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+ else
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+ return (1 << nb) - 1;
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+}
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+
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+
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void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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{
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if (cc->early_setup_done)
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@@ -87,8 +109,23 @@ void bcma_core_chipcommon_init(struct bc
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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{
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- /* instant NMI */
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- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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+ u32 maxt;
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+ enum bcma_clkmode clkmode;
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+
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+ maxt = bcma_chipco_watchdog_get_max_timer(cc);
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+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
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+ if (ticks == 1)
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+ ticks = 2;
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+ else if (ticks > maxt)
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+ ticks = maxt;
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+ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
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+ } else {
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+ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
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+ bcma_core_set_clockmode(cc->core, clkmode);
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+ if (ticks > maxt)
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+ ticks = maxt;
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+ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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+ }
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}
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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@ -1,93 +0,0 @@ |
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -10,6 +10,7 @@
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*/
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#include "bcma_private.h"
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+#include <linux/bcm47xx_wdt.h>
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#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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@@ -52,6 +53,39 @@ static u32 bcma_chipco_watchdog_get_max_
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return (1 << nb) - 1;
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}
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+static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
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+ u32 ticks)
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+{
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+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
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+
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+ return bcma_chipco_watchdog_timer_set(cc, ticks);
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+}
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+
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+static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
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+ u32 ms)
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+{
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+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
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+ u32 ticks;
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+
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+ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
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+ return ticks / cc->ticks_per_ms;
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+}
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+
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+static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
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+{
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+ struct bcma_bus *bus = cc->core->bus;
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+
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+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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+ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
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+ return bcma_chipco_alp_clock(cc) / 4000;
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+ else
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+ /* based on 32KHz ILP clock */
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+ return 32;
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+ } else {
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+ return bcma_chipco_alp_clock(cc) / 1000;
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+ }
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+}
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void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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{
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@@ -102,12 +136,13 @@ void bcma_core_chipcommon_init(struct bc
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}
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spin_lock_init(&cc->gpio_lock);
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+ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
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cc->setup_done = true;
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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+u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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{
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u32 maxt;
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enum bcma_clkmode clkmode;
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@@ -126,6 +161,7 @@ void bcma_chipco_watchdog_timer_set(stru
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ticks = maxt;
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bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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}
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+ return ticks;
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}
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -554,6 +554,7 @@ struct bcma_drv_cc {
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/* Lock for GPIO register access. */
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spinlock_t gpio_lock;
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+ u32 ticks_per_ms;
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};
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/* Register access */
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@@ -577,8 +578,7 @@ extern void bcma_chipco_resume(struct bc
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void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
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-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
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- u32 ticks);
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+extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
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@ -1,92 +0,0 @@ |
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -85,6 +85,8 @@ extern void __exit bcma_host_pci_exit(vo
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/* driver_pci.c */
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u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
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+extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
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+
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
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void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -12,6 +12,7 @@
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#include "bcma_private.h"
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#include <linux/bcm47xx_wdt.h>
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#include <linux/export.h>
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+#include <linux/platform_device.h>
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#include <linux/bcma/bcma.h>
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static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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@@ -87,6 +88,27 @@ static int bcma_chipco_watchdog_ticks_pe
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}
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}
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+int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
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+{
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+ struct bcm47xx_wdt wdt = {};
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+ struct platform_device *pdev;
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+
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+ wdt.driver_data = cc;
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+ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
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+ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
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+ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
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+
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+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
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+ cc->core->bus->num, &wdt,
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+ sizeof(wdt));
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+ if (IS_ERR(pdev))
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+ return PTR_ERR(pdev);
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+
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+ cc->watchdog = pdev;
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+
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+ return 0;
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+}
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+
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void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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{
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if (cc->early_setup_done)
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--- a/drivers/bcma/main.c
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+++ b/drivers/bcma/main.c
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@@ -173,6 +173,12 @@ static int bcma_register_cores(struct bc
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}
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#endif
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+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
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+ err = bcma_chipco_watchdog_register(&bus->drv_cc);
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+ if (err)
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+ bcma_err(bus, "Error registering watchdog driver\n");
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+ }
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+
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return 0;
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}
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@@ -185,6 +191,8 @@ static void bcma_unregister_cores(struct
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if (core->dev_registered)
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device_unregister(&core->dev);
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}
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+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
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+ platform_device_unregister(bus->drv_cc.watchdog);
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}
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int __devinit bcma_bus_register(struct bcma_bus *bus)
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -4,6 +4,8 @@
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#include <linux/mtd/bcm47xx_sflash.h>
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#include <linux/mtd/bcm47xx_nand.h>
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+#include <linux/platform_device.h>
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+
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/** ChipCommon core registers. **/
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#define BCMA_CC_ID 0x0000
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#define BCMA_CC_ID_ID 0x0000FFFF
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@@ -555,6 +557,7 @@ struct bcma_drv_cc {
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/* Lock for GPIO register access. */
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spinlock_t gpio_lock;
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u32 ticks_per_ms;
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+ struct platform_device *watchdog;
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};
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/* Register access */
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@ -1,76 +0,0 @@ |
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--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -280,6 +280,14 @@ static void calc_fast_powerup_delay(stru
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cc->fast_pwrup_delay = tmp;
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}
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+static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
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+{
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_alp_clock(cc);
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+
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+ return 20000000;
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+}
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+
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void ssb_chipcommon_init(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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@@ -474,11 +482,7 @@ int ssb_chipco_serial_init(struct ssb_ch
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| SSB_CHIPCO_CORECTL_UARTCLK0);
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} else if ((ccrev >= 11) && (ccrev != 15)) {
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/* Fixed ALP clock */
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- baud_base = 20000000;
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- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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- /* FIXME: baud_base is different for devices with a PMU */
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- SSB_WARN_ON(1);
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- }
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+ baud_base = ssb_chipco_alp_clock(cc);
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div = 1;
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if (ccrev >= 21) {
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/* Turn off UART clock before switching clocksource. */
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -618,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
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EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
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EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
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+static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
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+{
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+ u32 crystalfreq;
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+ const struct pmu0_plltab_entry *e = NULL;
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+
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+ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
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+ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
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+ e = pmu0_plltab_find_entry(crystalfreq);
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+ BUG_ON(!e);
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+ return e->freq * 1000;
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+}
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+
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+u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ ssb_pmu_get_alp_clock_clk0(cc);
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU alp clock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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+
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u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
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{
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struct ssb_bus *bus = cc->dev->bus;
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--- a/drivers/ssb/ssb_private.h
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+++ b/drivers/ssb/ssb_private.h
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@@ -210,6 +210,7 @@ static inline void b43_pci_ssb_bridge_ex
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/* driver_chipcommon_pmu.c */
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extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
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extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
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+extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
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#ifdef CONFIG_SSB_SFLASH
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/* driver_chipcommon_sflash.c */
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@ -1,54 +0,0 @@ |
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--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -288,6 +288,24 @@ static u32 ssb_chipco_alp_clock(struct s
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return 20000000;
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}
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+static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
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+{
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+ u32 nb;
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+
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ if (cc->dev->id.revision < 26)
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+ nb = 16;
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+ else
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+ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
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+ } else {
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+ nb = 28;
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+ }
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+ if (nb == 32)
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+ return 0xffffffff;
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+ else
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+ return (1 << nb) - 1;
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+}
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+
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void ssb_chipcommon_init(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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@@ -405,8 +423,24 @@ void ssb_chipco_timing_init(struct ssb_c
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
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{
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- /* instant NMI */
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- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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+ u32 maxt;
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+ enum ssb_clkmode clkmode;
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+
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+ maxt = ssb_chipco_watchdog_get_max_timer(cc);
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ if (ticks == 1)
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+ ticks = 2;
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+ else if (ticks > maxt)
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+ ticks = maxt;
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+ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
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+ } else {
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+ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
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+ ssb_chipco_set_clockmode(cc, clkmode);
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+ if (ticks > maxt)
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+ ticks = maxt;
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+ /* instant NMI */
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+ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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+ }
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}
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void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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@ -1,131 +0,0 @@ |
||||
--- a/drivers/ssb/driver_chipcommon.c
|
||||
+++ b/drivers/ssb/driver_chipcommon.c
|
||||
@@ -4,6 +4,7 @@
|
||||
*
|
||||
* Copyright 2005, Broadcom Corporation
|
||||
* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
|
||||
+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
@@ -12,6 +13,7 @@
|
||||
#include <linux/ssb/ssb_regs.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/pci.h>
|
||||
+#include <linux/bcm47xx_wdt.h>
|
||||
|
||||
#include "ssb_private.h"
|
||||
|
||||
@@ -306,6 +308,43 @@ static u32 ssb_chipco_watchdog_get_max_t
|
||||
return (1 << nb) - 1;
|
||||
}
|
||||
|
||||
+u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
|
||||
+{
|
||||
+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+
|
||||
+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
|
||||
+ return 0;
|
||||
+
|
||||
+ return ssb_chipco_watchdog_timer_set(cc, ticks);
|
||||
+}
|
||||
+
|
||||
+u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
|
||||
+{
|
||||
+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+ u32 ticks;
|
||||
+
|
||||
+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
|
||||
+ return 0;
|
||||
+
|
||||
+ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
|
||||
+ return ticks / cc->ticks_per_ms;
|
||||
+}
|
||||
+
|
||||
+static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
|
||||
+{
|
||||
+ struct ssb_bus *bus = cc->dev->bus;
|
||||
+
|
||||
+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
||||
+ /* based on 32KHz ILP clock */
|
||||
+ return 32;
|
||||
+ } else {
|
||||
+ if (cc->dev->id.revision < 18)
|
||||
+ return ssb_clockspeed(bus) / 1000;
|
||||
+ else
|
||||
+ return ssb_chipco_alp_clock(cc) / 1000;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
void ssb_chipcommon_init(struct ssb_chipcommon *cc)
|
||||
{
|
||||
if (!cc->dev)
|
||||
@@ -323,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
|
||||
chipco_powercontrol_init(cc);
|
||||
ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
|
||||
calc_fast_powerup_delay(cc);
|
||||
+
|
||||
+ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
|
||||
+ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
|
||||
+ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
|
||||
+ }
|
||||
}
|
||||
|
||||
void ssb_chipco_suspend(struct ssb_chipcommon *cc)
|
||||
@@ -421,7 +465,7 @@ void ssb_chipco_timing_init(struct ssb_c
|
||||
}
|
||||
|
||||
/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
|
||||
-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
|
||||
+u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
|
||||
{
|
||||
u32 maxt;
|
||||
enum ssb_clkmode clkmode;
|
||||
@@ -441,6 +485,7 @@ void ssb_chipco_watchdog_timer_set(struc
|
||||
/* instant NMI */
|
||||
chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
|
||||
}
|
||||
+ return ticks;
|
||||
}
|
||||
|
||||
void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
||||
--- a/drivers/ssb/ssb_private.h
|
||||
+++ b/drivers/ssb/ssb_private.h
|
||||
@@ -3,6 +3,7 @@
|
||||
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/types.h>
|
||||
+#include <linux/bcm47xx_wdt.h>
|
||||
|
||||
|
||||
#define PFX "ssb: "
|
||||
@@ -226,4 +227,8 @@ static inline int ssb_sflash_init(struct
|
||||
|
||||
extern struct platform_device ssb_pflash_dev;
|
||||
|
||||
+extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ticks);
|
||||
+extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
||||
+
|
||||
#endif /* LINUX_SSB_PRIVATE_H_ */
|
||||
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
||||
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
||||
@@ -607,6 +607,8 @@ struct ssb_chipcommon {
|
||||
#ifdef CONFIG_SSB_SFLASH
|
||||
struct bcm47xx_sflash sflash;
|
||||
#endif
|
||||
+ u32 ticks_per_ms;
|
||||
+ u32 max_timer_ms;
|
||||
};
|
||||
|
||||
static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
|
||||
@@ -646,8 +648,7 @@ enum ssb_clkmode {
|
||||
extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
|
||||
enum ssb_clkmode mode);
|
||||
|
||||
-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
|
||||
- u32 ticks);
|
||||
+extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
|
||||
|
||||
void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
||||
|
@ -1,25 +0,0 @@ |
||||
--- a/drivers/ssb/driver_extif.c
|
||||
+++ b/drivers/ssb/driver_extif.c
|
||||
@@ -112,9 +112,10 @@ void ssb_extif_get_clockcontrol(struct s
|
||||
*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
|
||||
}
|
||||
|
||||
-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
||||
- u32 ticks)
|
||||
+void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
|
||||
{
|
||||
+ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
|
||||
+ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
|
||||
extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
|
||||
}
|
||||
|
||||
--- a/include/linux/ssb/ssb_driver_extif.h
|
||||
+++ b/include/linux/ssb/ssb_driver_extif.h
|
||||
@@ -152,6 +152,7 @@
|
||||
/* watchdog */
|
||||
#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
|
||||
|
||||
+#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
|
||||
|
||||
|
||||
#ifdef CONFIG_SSB_DRIVER_EXTIF
|
@ -1,89 +0,0 @@ |
||||
--- a/drivers/ssb/driver_extif.c
|
||||
+++ b/drivers/ssb/driver_extif.c
|
||||
@@ -112,11 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
|
||||
*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
|
||||
}
|
||||
|
||||
-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
|
||||
+u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
|
||||
+{
|
||||
+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+
|
||||
+ return ssb_extif_watchdog_timer_set(extif, ticks);
|
||||
+}
|
||||
+
|
||||
+u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
|
||||
+{
|
||||
+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
|
||||
+
|
||||
+ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
|
||||
+
|
||||
+ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
|
||||
+}
|
||||
+
|
||||
+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
|
||||
{
|
||||
if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
|
||||
ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
|
||||
extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
|
||||
+
|
||||
+ return ticks;
|
||||
}
|
||||
|
||||
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
|
||||
--- a/drivers/ssb/ssb_private.h
|
||||
+++ b/drivers/ssb/ssb_private.h
|
||||
@@ -231,4 +231,19 @@ extern u32 ssb_chipco_watchdog_timer_set
|
||||
u32 ticks);
|
||||
extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
||||
|
||||
+#ifdef CONFIG_SSB_DRIVER_EXTIF
|
||||
+extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
|
||||
+extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
||||
+#else
|
||||
+static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ticks)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ms)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
#endif /* LINUX_SSB_PRIVATE_H_ */
|
||||
--- a/include/linux/ssb/ssb_driver_extif.h
|
||||
+++ b/include/linux/ssb/ssb_driver_extif.h
|
||||
@@ -153,6 +153,8 @@
|
||||
#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
|
||||
|
||||
#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
|
||||
+#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
|
||||
+ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
|
||||
|
||||
|
||||
#ifdef CONFIG_SSB_DRIVER_EXTIF
|
||||
@@ -172,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
|
||||
extern void ssb_extif_timing_init(struct ssb_extif *extif,
|
||||
unsigned long ns);
|
||||
|
||||
-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
||||
- u32 ticks);
|
||||
+extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
|
||||
|
||||
/* Extif GPIO pin access */
|
||||
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
|
||||
@@ -206,9 +207,9 @@ void ssb_extif_get_clockcontrol(struct s
|
||||
}
|
||||
|
||||
static inline
|
||||
-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
||||
- u32 ticks)
|
||||
+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
|
||||
{
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SSB_DRIVER_EXTIF */
|
@ -1,122 +0,0 @@ |
||||
--- a/drivers/ssb/embedded.c
|
||||
+++ b/drivers/ssb/embedded.c
|
||||
@@ -4,11 +4,13 @@
|
||||
*
|
||||
* Copyright 2005-2008, Broadcom Corporation
|
||||
* Copyright 2006-2008, Michael Buesch <m@bues.ch>
|
||||
+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
#include <linux/export.h>
|
||||
+#include <linux/platform_device.h>
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/ssb/ssb_embedded.h>
|
||||
#include <linux/ssb/ssb_driver_pci.h>
|
||||
@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
|
||||
}
|
||||
EXPORT_SYMBOL(ssb_watchdog_timer_set);
|
||||
|
||||
+int ssb_watchdog_register(struct ssb_bus *bus)
|
||||
+{
|
||||
+ struct bcm47xx_wdt wdt = {};
|
||||
+ struct platform_device *pdev;
|
||||
+
|
||||
+ if (ssb_chipco_available(&bus->chipco)) {
|
||||
+ wdt.driver_data = &bus->chipco;
|
||||
+ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
|
||||
+ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
|
||||
+ wdt.max_timer_ms = bus->chipco.max_timer_ms;
|
||||
+ } else if (ssb_extif_available(&bus->extif)) {
|
||||
+ wdt.driver_data = &bus->extif;
|
||||
+ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
|
||||
+ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
|
||||
+ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
|
||||
+ } else {
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
|
||||
+ bus->busnumber, &wdt,
|
||||
+ sizeof(wdt));
|
||||
+ if (IS_ERR(pdev)) {
|
||||
+ ssb_dprintk(KERN_INFO PFX
|
||||
+ "can not register watchdog device, err: %li\n",
|
||||
+ PTR_ERR(pdev));
|
||||
+ return PTR_ERR(pdev);
|
||||
+ }
|
||||
+
|
||||
+ bus->watchdog = pdev;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
--- a/drivers/ssb/main.c
|
||||
+++ b/drivers/ssb/main.c
|
||||
@@ -13,6 +13,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
+#include <linux/platform_device.h>
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/ssb/ssb_regs.h>
|
||||
#include <linux/ssb/ssb_driver_gige.h>
|
||||
@@ -434,6 +435,11 @@ static void ssb_devices_unregister(struc
|
||||
if (sdev->dev)
|
||||
device_unregister(sdev->dev);
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_SSB_EMBEDDED
|
||||
+ if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
+ platform_device_unregister(bus->watchdog);
|
||||
+#endif
|
||||
}
|
||||
|
||||
void ssb_bus_unregister(struct ssb_bus *bus)
|
||||
@@ -579,6 +585,8 @@ static int __devinit ssb_attach_queued_b
|
||||
if (err)
|
||||
goto error;
|
||||
ssb_pcicore_init(&bus->pcicore);
|
||||
+ if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
+ ssb_watchdog_register(bus);
|
||||
ssb_bus_may_powerdown(bus);
|
||||
|
||||
err = ssb_devices_register(bus);
|
||||
--- a/drivers/ssb/ssb_private.h
|
||||
+++ b/drivers/ssb/ssb_private.h
|
||||
@@ -246,4 +246,14 @@ static inline u32 ssb_extif_watchdog_tim
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
+
|
||||
+#ifdef CONFIG_SSB_EMBEDDED
|
||||
+extern int ssb_watchdog_register(struct ssb_bus *bus);
|
||||
+#else /* CONFIG_SSB_EMBEDDED */
|
||||
+static inline int ssb_watchdog_register(struct ssb_bus *bus)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif /* CONFIG_SSB_EMBEDDED */
|
||||
+
|
||||
#endif /* LINUX_SSB_PRIVATE_H_ */
|
||||
--- a/include/linux/ssb/ssb.h
|
||||
+++ b/include/linux/ssb/ssb.h
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <linux/pci.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
+#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/ssb/ssb_regs.h>
|
||||
|
||||
@@ -432,6 +433,7 @@ struct ssb_bus {
|
||||
#ifdef CONFIG_SSB_EMBEDDED
|
||||
/* Lock for GPIO register access. */
|
||||
spinlock_t gpio_lock;
|
||||
+ struct platform_device *watchdog;
|
||||
#endif /* EMBEDDED */
|
||||
|
||||
/* Internal-only stuff follows. Do not touch. */
|
@ -1,10 +0,0 @@ |
||||
--- a/drivers/ssb/b43_pci_bridge.c
|
||||
+++ b/drivers/ssb/b43_pci_bridge.c
|
||||
@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
|
||||
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
|
||||
{ 0, },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
|
@ -0,0 +1,22 @@ |
||||
--- /dev/null
|
||||
+++ b/include/linux/bcm47xx_wdt.h
|
||||
@@ -0,0 +1,19 @@
|
||||
+#ifndef LINUX_BCM47XX_WDT_H_
|
||||
+#define LINUX_BCM47XX_WDT_H_
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+
|
||||
+
|
||||
+struct bcm47xx_wdt {
|
||||
+ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
|
||||
+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
|
||||
+ u32 max_timer_ms;
|
||||
+
|
||||
+ void *driver_data;
|
||||
+};
|
||||
+
|
||||
+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
|
||||
+{
|
||||
+ return wdt->driver_data;
|
||||
+}
|
||||
+#endif /* LINUX_BCM47XX_WDT_H_ */
|
@ -1,19 +0,0 @@ |
||||
--- a/drivers/ssb/driver_chipcommon_pmu.c
|
||||
+++ b/drivers/ssb/driver_chipcommon_pmu.c
|
||||
@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
|
||||
chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
|
||||
}
|
||||
break;
|
||||
+ case 43222:
|
||||
+ break;
|
||||
default:
|
||||
ssb_printk(KERN_ERR PFX
|
||||
"ERROR: PLL init unknown for device %04X\n",
|
||||
@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
|
||||
min_msk = 0xCBB;
|
||||
break;
|
||||
case 0x4322:
|
||||
+ case 43222:
|
||||
/* We keep the default settings:
|
||||
* min_msk = 0xCBB
|
||||
* max_msk = 0x7FFFF
|
@ -1,10 +0,0 @@ |
||||
--- a/drivers/ssb/b43_pci_bridge.c
|
||||
+++ b/drivers/ssb/b43_pci_bridge.c
|
||||
@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
|
||||
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
|
||||
{ 0, },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
|
@ -0,0 +1,22 @@ |
||||
--- /dev/null
|
||||
+++ b/include/linux/bcm47xx_wdt.h
|
||||
@@ -0,0 +1,19 @@
|
||||
+#ifndef LINUX_BCM47XX_WDT_H_
|
||||
+#define LINUX_BCM47XX_WDT_H_
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+
|
||||
+
|
||||
+struct bcm47xx_wdt {
|
||||
+ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
|
||||
+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
|
||||
+ u32 max_timer_ms;
|
||||
+
|
||||
+ void *driver_data;
|
||||
+};
|
||||
+
|
||||
+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
|
||||
+{
|
||||
+ return wdt->driver_data;
|
||||
+}
|
||||
+#endif /* LINUX_BCM47XX_WDT_H_ */
|
@ -1,19 +0,0 @@ |
||||
--- a/drivers/ssb/driver_chipcommon_pmu.c
|
||||
+++ b/drivers/ssb/driver_chipcommon_pmu.c
|
||||
@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
|
||||
chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
|
||||
}
|
||||
break;
|
||||
+ case 43222:
|
||||
+ break;
|
||||
default:
|
||||
ssb_printk(KERN_ERR PFX
|
||||
"ERROR: PLL init unknown for device %04X\n",
|
||||
@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
|
||||
min_msk = 0xCBB;
|
||||
break;
|
||||
case 0x4322:
|
||||
+ case 43222:
|
||||
/* We keep the default settings:
|
||||
* min_msk = 0xCBB
|
||||
* max_msk = 0x7FFFF
|
@ -0,0 +1,612 @@ |
||||
--- a/drivers/ssb/b43_pci_bridge.c
|
||||
+++ b/drivers/ssb/b43_pci_bridge.c
|
||||
@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
|
||||
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
|
||||
{ 0, },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
|
||||
--- a/drivers/ssb/driver_chipcommon.c
|
||||
+++ b/drivers/ssb/driver_chipcommon.c
|
||||
@@ -4,6 +4,7 @@
|
||||
*
|
||||
* Copyright 2005, Broadcom Corporation
|
||||
* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
|
||||
+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
@@ -12,6 +13,7 @@
|
||||
#include <linux/ssb/ssb_regs.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/pci.h>
|
||||
+#include <linux/bcm47xx_wdt.h>
|
||||
|
||||
#include "ssb_private.h"
|
||||
|
||||
@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
|
||||
cc->fast_pwrup_delay = tmp;
|
||||
}
|
||||
|
||||
+static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
|
||||
+{
|
||||
+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
|
||||
+ return ssb_pmu_get_alp_clock(cc);
|
||||
+
|
||||
+ return 20000000;
|
||||
+}
|
||||
+
|
||||
+static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
|
||||
+{
|
||||
+ u32 nb;
|
||||
+
|
||||
+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
||||
+ if (cc->dev->id.revision < 26)
|
||||
+ nb = 16;
|
||||
+ else
|
||||
+ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
|
||||
+ } else {
|
||||
+ nb = 28;
|
||||
+ }
|
||||
+ if (nb == 32)
|
||||
+ return 0xffffffff;
|
||||
+ else
|
||||
+ return (1 << nb) - 1;
|
||||
+}
|
||||
+
|
||||
+u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
|
||||
+{
|
||||
+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+
|
||||
+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
|
||||
+ return 0;
|
||||
+
|
||||
+ return ssb_chipco_watchdog_timer_set(cc, ticks);
|
||||
+}
|
||||
+
|
||||
+u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
|
||||
+{
|
||||
+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+ u32 ticks;
|
||||
+
|
||||
+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
|
||||
+ return 0;
|
||||
+
|
||||
+ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
|
||||
+ return ticks / cc->ticks_per_ms;
|
||||
+}
|
||||
+
|
||||
+static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
|
||||
+{
|
||||
+ struct ssb_bus *bus = cc->dev->bus;
|
||||
+
|
||||
+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
||||
+ /* based on 32KHz ILP clock */
|
||||
+ return 32;
|
||||
+ } else {
|
||||
+ if (cc->dev->id.revision < 18)
|
||||
+ return ssb_clockspeed(bus) / 1000;
|
||||
+ else
|
||||
+ return ssb_chipco_alp_clock(cc) / 1000;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
void ssb_chipcommon_init(struct ssb_chipcommon *cc)
|
||||
{
|
||||
if (!cc->dev)
|
||||
@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
|
||||
chipco_powercontrol_init(cc);
|
||||
ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
|
||||
calc_fast_powerup_delay(cc);
|
||||
+
|
||||
+ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
|
||||
+ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
|
||||
+ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
|
||||
+ }
|
||||
}
|
||||
|
||||
void ssb_chipco_suspend(struct ssb_chipcommon *cc)
|
||||
@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
|
||||
}
|
||||
|
||||
/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
|
||||
-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
|
||||
+u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
|
||||
{
|
||||
- /* instant NMI */
|
||||
- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
|
||||
+ u32 maxt;
|
||||
+ enum ssb_clkmode clkmode;
|
||||
+
|
||||
+ maxt = ssb_chipco_watchdog_get_max_timer(cc);
|
||||
+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
||||
+ if (ticks == 1)
|
||||
+ ticks = 2;
|
||||
+ else if (ticks > maxt)
|
||||
+ ticks = maxt;
|
||||
+ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
|
||||
+ } else {
|
||||
+ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
|
||||
+ ssb_chipco_set_clockmode(cc, clkmode);
|
||||
+ if (ticks > maxt)
|
||||
+ ticks = maxt;
|
||||
+ /* instant NMI */
|
||||
+ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
|
||||
+ }
|
||||
+ return ticks;
|
||||
}
|
||||
|
||||
void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
||||
@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
|
||||
chipco_read32(cc, SSB_CHIPCO_CORECTL)
|
||||
| SSB_CHIPCO_CORECTL_UARTCLK0);
|
||||
} else if ((ccrev >= 11) && (ccrev != 15)) {
|
||||
- /* Fixed ALP clock */
|
||||
- baud_base = 20000000;
|
||||
- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
||||
- /* FIXME: baud_base is different for devices with a PMU */
|
||||
- SSB_WARN_ON(1);
|
||||
- }
|
||||
+ baud_base = ssb_chipco_alp_clock(cc);
|
||||
div = 1;
|
||||
if (ccrev >= 21) {
|
||||
/* Turn off UART clock before switching clocksource. */
|
||||
--- a/drivers/ssb/driver_chipcommon_pmu.c
|
||||
+++ b/drivers/ssb/driver_chipcommon_pmu.c
|
||||
@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
|
||||
chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
|
||||
}
|
||||
break;
|
||||
+ case 43222:
|
||||
+ break;
|
||||
default:
|
||||
ssb_printk(KERN_ERR PFX
|
||||
"ERROR: PLL init unknown for device %04X\n",
|
||||
@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
|
||||
min_msk = 0xCBB;
|
||||
break;
|
||||
case 0x4322:
|
||||
+ case 43222:
|
||||
/* We keep the default settings:
|
||||
* min_msk = 0xCBB
|
||||
* max_msk = 0x7FFFF
|
||||
@@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
|
||||
EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
|
||||
EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
|
||||
|
||||
+static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
|
||||
+{
|
||||
+ u32 crystalfreq;
|
||||
+ const struct pmu0_plltab_entry *e = NULL;
|
||||
+
|
||||
+ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
|
||||
+ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
|
||||
+ e = pmu0_plltab_find_entry(crystalfreq);
|
||||
+ BUG_ON(!e);
|
||||
+ return e->freq * 1000;
|
||||
+}
|
||||
+
|
||||
+u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
|
||||
+{
|
||||
+ struct ssb_bus *bus = cc->dev->bus;
|
||||
+
|
||||
+ switch (bus->chip_id) {
|
||||
+ case 0x5354:
|
||||
+ ssb_pmu_get_alp_clock_clk0(cc);
|
||||
+ default:
|
||||
+ ssb_printk(KERN_ERR PFX
|
||||
+ "ERROR: PMU alp clock unknown for device %04X\n",
|
||||
+ bus->chip_id);
|
||||
+ return 0;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
|
||||
{
|
||||
struct ssb_bus *bus = cc->dev->bus;
|
||||
--- a/drivers/ssb/driver_extif.c
|
||||
+++ b/drivers/ssb/driver_extif.c
|
||||
@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
|
||||
*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
|
||||
}
|
||||
|
||||
-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
||||
- u32 ticks)
|
||||
+u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
|
||||
{
|
||||
+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+
|
||||
+ return ssb_extif_watchdog_timer_set(extif, ticks);
|
||||
+}
|
||||
+
|
||||
+u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
|
||||
+{
|
||||
+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
|
||||
+
|
||||
+ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
|
||||
+
|
||||
+ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
|
||||
+}
|
||||
+
|
||||
+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
|
||||
+{
|
||||
+ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
|
||||
+ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
|
||||
extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
|
||||
+
|
||||
+ return ticks;
|
||||
}
|
||||
|
||||
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
|
||||
--- a/drivers/ssb/driver_mipscore.c
|
||||
+++ b/drivers/ssb/driver_mipscore.c
|
||||
@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
|
||||
{
|
||||
struct ssb_bus *bus = mcore->dev->bus;
|
||||
|
||||
- if (bus->extif.dev)
|
||||
+ if (ssb_extif_available(&bus->extif))
|
||||
mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
|
||||
- else if (bus->chipco.dev)
|
||||
+ else if (ssb_chipco_available(&bus->chipco))
|
||||
mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
|
||||
else
|
||||
mcore->nr_serial_ports = 0;
|
||||
@@ -191,10 +191,11 @@ static void ssb_mips_flash_detect(struct
|
||||
struct ssb_bus *bus = mcore->dev->bus;
|
||||
|
||||
/* When there is no chipcommon on the bus there is 4MB flash */
|
||||
- if (!bus->chipco.dev) {
|
||||
- mcore->flash_buswidth = 2;
|
||||
- mcore->flash_window = SSB_FLASH1;
|
||||
- mcore->flash_window_size = SSB_FLASH1_SZ;
|
||||
+ if (!ssb_chipco_available(&bus->chipco)) {
|
||||
+ mcore->pflash.present = true;
|
||||
+ mcore->pflash.buswidth = 2;
|
||||
+ mcore->pflash.window = SSB_FLASH1;
|
||||
+ mcore->pflash.window_size = SSB_FLASH1_SZ;
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -206,13 +207,14 @@ static void ssb_mips_flash_detect(struct
|
||||
break;
|
||||
case SSB_CHIPCO_FLASHT_PARA:
|
||||
pr_debug("Found parallel flash\n");
|
||||
- mcore->flash_window = SSB_FLASH2;
|
||||
- mcore->flash_window_size = SSB_FLASH2_SZ;
|
||||
+ mcore->pflash.present = true;
|
||||
+ mcore->pflash.window = SSB_FLASH2;
|
||||
+ mcore->pflash.window_size = SSB_FLASH2_SZ;
|
||||
if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
|
||||
& SSB_CHIPCO_CFG_DS16) == 0)
|
||||
- mcore->flash_buswidth = 1;
|
||||
+ mcore->pflash.buswidth = 1;
|
||||
else
|
||||
- mcore->flash_buswidth = 2;
|
||||
+ mcore->pflash.buswidth = 2;
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -225,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
|
||||
if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
|
||||
return ssb_pmu_get_cpu_clock(&bus->chipco);
|
||||
|
||||
- if (bus->extif.dev) {
|
||||
+ if (ssb_extif_available(&bus->extif)) {
|
||||
ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
|
||||
- } else if (bus->chipco.dev) {
|
||||
+ } else if (ssb_chipco_available(&bus->chipco)) {
|
||||
ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
|
||||
} else
|
||||
return 0;
|
||||
@@ -263,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
|
||||
hz = 100000000;
|
||||
ns = 1000000000 / hz;
|
||||
|
||||
- if (bus->extif.dev)
|
||||
+ if (ssb_extif_available(&bus->extif))
|
||||
ssb_extif_timing_init(&bus->extif, ns);
|
||||
- else if (bus->chipco.dev)
|
||||
+ else if (ssb_chipco_available(&bus->chipco))
|
||||
ssb_chipco_timing_init(&bus->chipco, ns);
|
||||
|
||||
/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
|
||||
--- a/drivers/ssb/embedded.c
|
||||
+++ b/drivers/ssb/embedded.c
|
||||
@@ -4,11 +4,13 @@
|
||||
*
|
||||
* Copyright 2005-2008, Broadcom Corporation
|
||||
* Copyright 2006-2008, Michael Buesch <m@bues.ch>
|
||||
+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
#include <linux/export.h>
|
||||
+#include <linux/platform_device.h>
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/ssb/ssb_embedded.h>
|
||||
#include <linux/ssb/ssb_driver_pci.h>
|
||||
@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
|
||||
}
|
||||
EXPORT_SYMBOL(ssb_watchdog_timer_set);
|
||||
|
||||
+int ssb_watchdog_register(struct ssb_bus *bus)
|
||||
+{
|
||||
+ struct bcm47xx_wdt wdt = {};
|
||||
+ struct platform_device *pdev;
|
||||
+
|
||||
+ if (ssb_chipco_available(&bus->chipco)) {
|
||||
+ wdt.driver_data = &bus->chipco;
|
||||
+ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
|
||||
+ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
|
||||
+ wdt.max_timer_ms = bus->chipco.max_timer_ms;
|
||||
+ } else if (ssb_extif_available(&bus->extif)) {
|
||||
+ wdt.driver_data = &bus->extif;
|
||||
+ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
|
||||
+ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
|
||||
+ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
|
||||
+ } else {
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
|
||||
+ bus->busnumber, &wdt,
|
||||
+ sizeof(wdt));
|
||||
+ if (IS_ERR(pdev)) {
|
||||
+ ssb_dprintk(KERN_INFO PFX
|
||||
+ "can not register watchdog device, err: %li\n",
|
||||
+ PTR_ERR(pdev));
|
||||
+ return PTR_ERR(pdev);
|
||||
+ }
|
||||
+
|
||||
+ bus->watchdog = pdev;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
--- a/drivers/ssb/main.c
|
||||
+++ b/drivers/ssb/main.c
|
||||
@@ -13,6 +13,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
+#include <linux/platform_device.h>
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/ssb/ssb_regs.h>
|
||||
#include <linux/ssb/ssb_driver_gige.h>
|
||||
@@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
|
||||
if (sdev->dev)
|
||||
device_unregister(sdev->dev);
|
||||
}
|
||||
+
|
||||
+#ifdef CONFIG_SSB_EMBEDDED
|
||||
+ if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
+ platform_device_unregister(bus->watchdog);
|
||||
+#endif
|
||||
}
|
||||
|
||||
void ssb_bus_unregister(struct ssb_bus *bus)
|
||||
@@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
|
||||
if (err)
|
||||
goto error;
|
||||
ssb_pcicore_init(&bus->pcicore);
|
||||
+ if (bus->bustype == SSB_BUSTYPE_SSB)
|
||||
+ ssb_watchdog_register(bus);
|
||||
ssb_bus_may_powerdown(bus);
|
||||
|
||||
err = ssb_devices_register(bus);
|
||||
@@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
|
||||
case SSB_IDLOW_SSBREV_27: /* same here */
|
||||
return SSB_TMSLOW_REJECT; /* this is a guess */
|
||||
default:
|
||||
- printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
|
||||
- WARN_ON(1);
|
||||
+ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
|
||||
}
|
||||
return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
|
||||
}
|
||||
--- a/drivers/ssb/ssb_private.h
|
||||
+++ b/drivers/ssb/ssb_private.h
|
||||
@@ -3,6 +3,7 @@
|
||||
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/types.h>
|
||||
+#include <linux/bcm47xx_wdt.h>
|
||||
|
||||
|
||||
#define PFX "ssb: "
|
||||
@@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex
|
||||
/* driver_chipcommon_pmu.c */
|
||||
extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
|
||||
extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
|
||||
+extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
|
||||
+
|
||||
+extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ticks);
|
||||
+extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
||||
+
|
||||
+#ifdef CONFIG_SSB_DRIVER_EXTIF
|
||||
+extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
|
||||
+extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
||||
+#else
|
||||
+static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ticks)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ms)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+#ifdef CONFIG_SSB_EMBEDDED
|
||||
+extern int ssb_watchdog_register(struct ssb_bus *bus);
|
||||
+#else /* CONFIG_SSB_EMBEDDED */
|
||||
+static inline int ssb_watchdog_register(struct ssb_bus *bus)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif /* CONFIG_SSB_EMBEDDED */
|
||||
|
||||
#endif /* LINUX_SSB_PRIVATE_H_ */
|
||||
--- a/include/linux/ssb/ssb.h
|
||||
+++ b/include/linux/ssb/ssb.h
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <linux/pci.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
+#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/ssb/ssb_regs.h>
|
||||
|
||||
@@ -432,6 +433,7 @@ struct ssb_bus {
|
||||
#ifdef CONFIG_SSB_EMBEDDED
|
||||
/* Lock for GPIO register access. */
|
||||
spinlock_t gpio_lock;
|
||||
+ struct platform_device *watchdog;
|
||||
#endif /* EMBEDDED */
|
||||
|
||||
/* Internal-only stuff follows. Do not touch. */
|
||||
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
||||
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
||||
@@ -591,6 +591,8 @@ struct ssb_chipcommon {
|
||||
/* Fast Powerup Delay constant */
|
||||
u16 fast_pwrup_delay;
|
||||
struct ssb_chipcommon_pmu pmu;
|
||||
+ u32 ticks_per_ms;
|
||||
+ u32 max_timer_ms;
|
||||
};
|
||||
|
||||
static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
|
||||
@@ -630,8 +632,7 @@ enum ssb_clkmode {
|
||||
extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
|
||||
enum ssb_clkmode mode);
|
||||
|
||||
-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
|
||||
- u32 ticks);
|
||||
+extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
|
||||
|
||||
void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
||||
|
||||
--- a/include/linux/ssb/ssb_driver_extif.h
|
||||
+++ b/include/linux/ssb/ssb_driver_extif.h
|
||||
@@ -152,6 +152,9 @@
|
||||
/* watchdog */
|
||||
#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
|
||||
|
||||
+#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
|
||||
+#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
|
||||
+ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
|
||||
|
||||
|
||||
#ifdef CONFIG_SSB_DRIVER_EXTIF
|
||||
@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
|
||||
extern void ssb_extif_timing_init(struct ssb_extif *extif,
|
||||
unsigned long ns);
|
||||
|
||||
-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
||||
- u32 ticks);
|
||||
+extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
|
||||
|
||||
/* Extif GPIO pin access */
|
||||
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
|
||||
@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
|
||||
}
|
||||
|
||||
static inline
|
||||
-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
||||
- u32 ticks)
|
||||
+void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
|
||||
{
|
||||
}
|
||||
|
||||
+static inline
|
||||
+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
|
||||
+ u32 value)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
|
||||
+ u32 value)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
|
||||
+ u32 value)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
|
||||
+ u32 value)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_SSB_SERIAL
|
||||
+static inline int ssb_extif_serial_init(struct ssb_extif *extif,
|
||||
+ struct ssb_serial_port *ports)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif /* CONFIG_SSB_SERIAL */
|
||||
+
|
||||
#endif /* CONFIG_SSB_DRIVER_EXTIF */
|
||||
#endif /* LINUX_SSB_EXTIFCORE_H_ */
|
||||
--- a/include/linux/ssb/ssb_driver_mips.h
|
||||
+++ b/include/linux/ssb/ssb_driver_mips.h
|
||||
@@ -13,6 +13,12 @@ struct ssb_serial_port {
|
||||
unsigned int reg_shift;
|
||||
};
|
||||
|
||||
+struct ssb_pflash {
|
||||
+ bool present;
|
||||
+ u8 buswidth;
|
||||
+ u32 window;
|
||||
+ u32 window_size;
|
||||
+};
|
||||
|
||||
struct ssb_mipscore {
|
||||
struct ssb_device *dev;
|
||||
@@ -20,9 +26,7 @@ struct ssb_mipscore {
|
||||
int nr_serial_ports;
|
||||
struct ssb_serial_port serial_ports[4];
|
||||
|
||||
- u8 flash_buswidth;
|
||||
- u32 flash_window;
|
||||
- u32 flash_window_size;
|
||||
+ struct ssb_pflash pflash;
|
||||
};
|
||||
|
||||
extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
|
||||
--- a/include/linux/ssb/ssb_regs.h
|
||||
+++ b/include/linux/ssb/ssb_regs.h
|
||||
@@ -485,7 +485,7 @@
|
||||
#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
|
||||
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
|
||||
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
|
||||
-#define SSB_SPROM8_TEMPDELTA 0x00BA
|
||||
+#define SSB_SPROM8_TEMPDELTA 0x00BC
|
||||
#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
|
||||
#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
|
||||
#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
|
@ -1,10 +0,0 @@ |
||||
--- a/drivers/ssb/b43_pci_bridge.c
|
||||
+++ b/drivers/ssb/b43_pci_bridge.c
|
||||
@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
|
||||
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
|
||||
{ 0, },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
|
@ -0,0 +1,22 @@ |
||||
--- /dev/null
|
||||
+++ b/include/linux/bcm47xx_wdt.h
|
||||
@@ -0,0 +1,19 @@
|
||||
+#ifndef LINUX_BCM47XX_WDT_H_
|
||||
+#define LINUX_BCM47XX_WDT_H_
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+
|
||||
+
|
||||
+struct bcm47xx_wdt {
|
||||
+ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
|
||||
+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
|
||||
+ u32 max_timer_ms;
|
||||
+
|
||||
+ void *driver_data;
|
||||
+};
|
||||
+
|
||||
+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
|
||||
+{
|
||||
+ return wdt->driver_data;
|
||||
+}
|
||||
+#endif /* LINUX_BCM47XX_WDT_H_ */
|
@ -1,19 +0,0 @@ |
||||
--- a/drivers/ssb/driver_chipcommon_pmu.c
|
||||
+++ b/drivers/ssb/driver_chipcommon_pmu.c
|
||||
@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
|
||||
chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
|
||||
}
|
||||
break;
|
||||
+ case 43222:
|
||||
+ break;
|
||||
default:
|
||||
ssb_printk(KERN_ERR PFX
|
||||
"ERROR: PLL init unknown for device %04X\n",
|
||||
@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
|
||||
min_msk = 0xCBB;
|
||||
break;
|
||||
case 0x4322:
|
||||
+ case 43222:
|
||||
/* We keep the default settings:
|
||||
* min_msk = 0xCBB
|
||||
* max_msk = 0x7FFFF
|
@ -0,0 +1,971 @@ |
||||
--- a/arch/mips/bcm47xx/nvram.c
|
||||
+++ b/arch/mips/bcm47xx/nvram.c
|
||||
@@ -43,8 +43,8 @@ static void early_nvram_init(void)
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
case BCM47XX_BUS_TYPE_SSB:
|
||||
mcore_ssb = &bcm47xx_bus.ssb.mipscore;
|
||||
- base = mcore_ssb->flash_window;
|
||||
- lim = mcore_ssb->flash_window_size;
|
||||
+ base = mcore_ssb->pflash.window;
|
||||
+ lim = mcore_ssb->pflash.window_size;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
--- a/arch/mips/bcm47xx/wgt634u.c
|
||||
+++ b/arch/mips/bcm47xx/wgt634u.c
|
||||
@@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
|
||||
SSB_CHIPCO_IRQ_GPIO);
|
||||
}
|
||||
|
||||
- wgt634u_flash_data.width = mcore->flash_buswidth;
|
||||
- wgt634u_flash_resource.start = mcore->flash_window;
|
||||
- wgt634u_flash_resource.end = mcore->flash_window
|
||||
- + mcore->flash_window_size
|
||||
+ wgt634u_flash_data.width = mcore->pflash.buswidth;
|
||||
+ wgt634u_flash_resource.start = mcore->pflash.window;
|
||||
+ wgt634u_flash_resource.end = mcore->pflash.window
|
||||
+ + mcore->pflash.window_size
|
||||
- 1;
|
||||
return platform_add_devices(wgt634u_devices,
|
||||
ARRAY_SIZE(wgt634u_devices));
|
||||
--- a/drivers/bcma/bcma_private.h
|
||||
+++ b/drivers/bcma/bcma_private.h
|
||||
@@ -48,8 +48,8 @@ void bcma_chipco_serial_init(struct bcma
|
||||
#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
||||
|
||||
/* driver_chipcommon_pmu.c */
|
||||
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
|
||||
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
|
||||
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
|
||||
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
|
||||
|
||||
#ifdef CONFIG_BCMA_SFLASH
|
||||
/* driver_chipcommon_sflash.c */
|
||||
@@ -84,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo
|
||||
/* driver_pci.c */
|
||||
u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
|
||||
|
||||
+extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
|
||||
+
|
||||
#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
|
||||
bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
|
||||
void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
|
||||
--- a/drivers/bcma/driver_chipcommon.c
|
||||
+++ b/drivers/bcma/driver_chipcommon.c
|
||||
@@ -4,12 +4,15 @@
|
||||
*
|
||||
* Copyright 2005, Broadcom Corporation
|
||||
* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
|
||||
+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
#include "bcma_private.h"
|
||||
+#include <linux/bcm47xx_wdt.h>
|
||||
#include <linux/export.h>
|
||||
+#include <linux/platform_device.h>
|
||||
#include <linux/bcma/bcma.h>
|
||||
|
||||
static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
|
||||
@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked
|
||||
return value;
|
||||
}
|
||||
|
||||
-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
|
||||
+static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
|
||||
{
|
||||
- u32 leddc_on = 10;
|
||||
- u32 leddc_off = 90;
|
||||
+ if (cc->capabilities & BCMA_CC_CAP_PMU)
|
||||
+ return bcma_pmu_get_alp_clock(cc);
|
||||
|
||||
- if (cc->setup_done)
|
||||
+ return 20000000;
|
||||
+}
|
||||
+
|
||||
+static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
|
||||
+{
|
||||
+ struct bcma_bus *bus = cc->core->bus;
|
||||
+ u32 nb;
|
||||
+
|
||||
+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
|
||||
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
|
||||
+ nb = 32;
|
||||
+ else if (cc->core->id.rev < 26)
|
||||
+ nb = 16;
|
||||
+ else
|
||||
+ nb = (cc->core->id.rev >= 37) ? 32 : 24;
|
||||
+ } else {
|
||||
+ nb = 28;
|
||||
+ }
|
||||
+ if (nb == 32)
|
||||
+ return 0xffffffff;
|
||||
+ else
|
||||
+ return (1 << nb) - 1;
|
||||
+}
|
||||
+
|
||||
+static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ticks)
|
||||
+{
|
||||
+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+
|
||||
+ return bcma_chipco_watchdog_timer_set(cc, ticks);
|
||||
+}
|
||||
+
|
||||
+static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
|
||||
+ u32 ms)
|
||||
+{
|
||||
+ struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
|
||||
+ u32 ticks;
|
||||
+
|
||||
+ ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
|
||||
+ return ticks / cc->ticks_per_ms;
|
||||
+}
|
||||
+
|
||||
+static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
|
||||
+{
|
||||
+ struct bcma_bus *bus = cc->core->bus;
|
||||
+
|
||||
+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
|
||||
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
|
||||
+ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
|
||||
+ return bcma_chipco_get_alp_clock(cc) / 4000;
|
||||
+ else
|
||||
+ /* based on 32KHz ILP clock */
|
||||
+ return 32;
|
||||
+ } else {
|
||||
+ return bcma_chipco_get_alp_clock(cc) / 1000;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
|
||||
+{
|
||||
+ struct bcm47xx_wdt wdt = {};
|
||||
+ struct platform_device *pdev;
|
||||
+
|
||||
+ wdt.driver_data = cc;
|
||||
+ wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
|
||||
+ wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
|
||||
+ wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
|
||||
+
|
||||
+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
|
||||
+ cc->core->bus->num, &wdt,
|
||||
+ sizeof(wdt));
|
||||
+ if (IS_ERR(pdev))
|
||||
+ return PTR_ERR(pdev);
|
||||
+
|
||||
+ cc->watchdog = pdev;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
|
||||
+{
|
||||
+ if (cc->early_setup_done)
|
||||
return;
|
||||
|
||||
if (cc->core->id.rev >= 11)
|
||||
@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc
|
||||
if (cc->core->id.rev >= 35)
|
||||
cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
|
||||
|
||||
+ if (cc->capabilities & BCMA_CC_CAP_PMU)
|
||||
+ bcma_pmu_early_init(cc);
|
||||
+
|
||||
+ cc->early_setup_done = true;
|
||||
+}
|
||||
+
|
||||
+void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
|
||||
+{
|
||||
+ u32 leddc_on = 10;
|
||||
+ u32 leddc_off = 90;
|
||||
+
|
||||
+ if (cc->setup_done)
|
||||
+ return;
|
||||
+
|
||||
+ bcma_core_chipcommon_early_init(cc);
|
||||
+
|
||||
if (cc->core->id.rev >= 20) {
|
||||
bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
|
||||
bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
|
||||
@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc
|
||||
((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
|
||||
(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
|
||||
}
|
||||
+ cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
|
||||
|
||||
cc->setup_done = true;
|
||||
}
|
||||
|
||||
/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
|
||||
-void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
|
||||
+u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
|
||||
{
|
||||
- /* instant NMI */
|
||||
- bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
|
||||
+ u32 maxt;
|
||||
+ enum bcma_clkmode clkmode;
|
||||
+
|
||||
+ maxt = bcma_chipco_watchdog_get_max_timer(cc);
|
||||
+ if (cc->capabilities & BCMA_CC_CAP_PMU) {
|
||||
+ if (ticks == 1)
|
||||
+ ticks = 2;
|
||||
+ else if (ticks > maxt)
|
||||
+ ticks = maxt;
|
||||
+ bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
|
||||
+ } else {
|
||||
+ clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
|
||||
+ bcma_core_set_clockmode(cc->core, clkmode);
|
||||
+ if (ticks > maxt)
|
||||
+ ticks = maxt;
|
||||
+ /* instant NMI */
|
||||
+ bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
|
||||
+ }
|
||||
+ return ticks;
|
||||
}
|
||||
|
||||
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
|
||||
@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma
|
||||
struct bcma_serial_port *ports = cc->serial_ports;
|
||||
|
||||
if (ccrev >= 11 && ccrev != 15) {
|
||||
- /* Fixed ALP clock */
|
||||
- baud_base = bcma_pmu_alp_clock(cc);
|
||||
+ baud_base = bcma_chipco_get_alp_clock(cc);
|
||||
if (ccrev >= 21) {
|
||||
/* Turn off UART clock before switching clocksource. */
|
||||
bcma_cc_write32(cc, BCMA_CC_CORECTL,
|
||||
--- a/drivers/bcma/driver_chipcommon_nflash.c
|
||||
+++ b/drivers/bcma/driver_chipcommon_nflash.c
|
||||
@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
|
||||
}
|
||||
|
||||
cc->nflash.present = true;
|
||||
+ if (cc->core->id.rev == 38 &&
|
||||
+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
|
||||
+ cc->nflash.boot = true;
|
||||
|
||||
/* Prepare platform device, but don't register it yet. It's too early,
|
||||
* malloc (required by device_private_init) is not available yet. */
|
||||
--- a/drivers/bcma/driver_chipcommon_pmu.c
|
||||
+++ b/drivers/bcma/driver_chipcommon_pmu.c
|
||||
@@ -144,7 +144,7 @@ static void bcma_pmu_workarounds(struct
|
||||
}
|
||||
}
|
||||
|
||||
-void bcma_pmu_init(struct bcma_drv_cc *cc)
|
||||
+void bcma_pmu_early_init(struct bcma_drv_cc *cc)
|
||||
{
|
||||
u32 pmucap;
|
||||
|
||||
@@ -153,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
|
||||
|
||||
bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
|
||||
cc->pmu.rev, pmucap);
|
||||
+}
|
||||
|
||||
+void bcma_pmu_init(struct bcma_drv_cc *cc)
|
||||
+{
|
||||
if (cc->pmu.rev == 1)
|
||||
bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
|
||||
~BCMA_CC_PMU_CTL_NOILPONW);
|
||||
@@ -165,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
|
||||
bcma_pmu_workarounds(cc);
|
||||
}
|
||||
|
||||
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
|
||||
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
|
||||
{
|
||||
struct bcma_bus *bus = cc->core->bus;
|
||||
|
||||
@@ -193,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
|
||||
/* Find the output of the "m" pll divider given pll controls that start with
|
||||
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
|
||||
*/
|
||||
-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
||||
+static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
||||
{
|
||||
u32 tmp, div, ndiv, p1, p2, fc;
|
||||
struct bcma_bus *bus = cc->core->bus;
|
||||
@@ -222,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
|
||||
ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
|
||||
|
||||
/* Do calculation in Mhz */
|
||||
- fc = bcma_pmu_alp_clock(cc) / 1000000;
|
||||
+ fc = bcma_pmu_get_alp_clock(cc) / 1000000;
|
||||
fc = (p1 * ndiv * fc) / p2;
|
||||
|
||||
/* Return clock in Hertz */
|
||||
return (fc / div) * 1000000;
|
||||
}
|
||||
|
||||
-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
||||
+static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
|
||||
{
|
||||
u32 tmp, ndiv, p1div, p2div;
|
||||
u32 clock;
|
||||
@@ -260,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
|
||||
}
|
||||
|
||||
/* query bus clock frequency for PMU-enabled chipcommon */
|
||||
-static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
|
||||
+static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
|
||||
{
|
||||
struct bcma_bus *bus = cc->core->bus;
|
||||
|
||||
@@ -268,40 +271,42 @@ static u32 bcma_pmu_get_clockcontrol(str
|
||||
case BCMA_CHIP_ID_BCM4716:
|
||||
case BCMA_CHIP_ID_BCM4748:
|
||||
case BCMA_CHIP_ID_BCM47162:
|
||||
- return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
|
||||
- BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
|
||||
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
case BCMA_CHIP_ID_BCM5356:
|
||||
- return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
|
||||
- BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
|
||||
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
case BCMA_CHIP_ID_BCM5357:
|
||||
case BCMA_CHIP_ID_BCM4749:
|
||||
- return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
|
||||
- BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
+ return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
|
||||
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
case BCMA_CHIP_ID_BCM4706:
|
||||
- return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
|
||||
- BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
+ return bcma_pmu_pll_clock_bcm4706(cc,
|
||||
+ BCMA_CC_PMU4706_MAINPLL_PLL0,
|
||||
+ BCMA_CC_PMU5_MAINPLL_SSB);
|
||||
case BCMA_CHIP_ID_BCM53572:
|
||||
return 75000000;
|
||||
default:
|
||||
- bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
|
||||
+ bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
|
||||
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
|
||||
}
|
||||
return BCMA_CC_PMU_HT_CLOCK;
|
||||
}
|
||||
|
||||
/* query cpu clock frequency for PMU-enabled chipcommon */
|
||||
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
|
||||
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
|
||||
{
|
||||
struct bcma_bus *bus = cc->core->bus;
|
||||
|
||||
if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
|
||||
return 300000000;
|
||||
|
||||
+ /* New PMUs can have different clock for bus and CPU */
|
||||
if (cc->pmu.rev >= 5) {
|
||||
u32 pll;
|
||||
switch (bus->chipinfo.id) {
|
||||
case BCMA_CHIP_ID_BCM4706:
|
||||
- return bcma_pmu_clock_bcm4706(cc,
|
||||
+ return bcma_pmu_pll_clock_bcm4706(cc,
|
||||
BCMA_CC_PMU4706_MAINPLL_PLL0,
|
||||
BCMA_CC_PMU5_MAINPLL_CPU);
|
||||
case BCMA_CHIP_ID_BCM5356:
|
||||
@@ -316,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
|
||||
break;
|
||||
}
|
||||
|
||||
- return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
||||
+ return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
||||
}
|
||||
|
||||
- return bcma_pmu_get_clockcontrol(cc);
|
||||
+ /* On old PMUs CPU has the same clock as the bus */
|
||||
+ return bcma_pmu_get_bus_clock(cc);
|
||||
}
|
||||
|
||||
static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
||||
--- a/drivers/bcma/driver_chipcommon_sflash.c
|
||||
+++ b/drivers/bcma/driver_chipcommon_sflash.c
|
||||
@@ -12,7 +12,7 @@
|
||||
|
||||
static struct resource bcma_sflash_resource = {
|
||||
.name = "bcma_sflash",
|
||||
- .start = BCMA_SFLASH,
|
||||
+ .start = BCMA_SOC_FLASH2,
|
||||
.end = 0,
|
||||
.flags = IORESOURCE_MEM | IORESOURCE_READONLY,
|
||||
};
|
||||
@@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e {
|
||||
};
|
||||
|
||||
static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
|
||||
- { "", 0x14, 0x10000, 32, },
|
||||
+ { "M25P20", 0x11, 0x10000, 4, },
|
||||
+ { "M25P40", 0x12, 0x10000, 8, },
|
||||
+
|
||||
+ { "M25P16", 0x14, 0x10000, 32, },
|
||||
+ { "M25P32", 0x14, 0x10000, 64, },
|
||||
+ { "M25P64", 0x16, 0x10000, 128, },
|
||||
+ { "M25FL128", 0x17, 0x10000, 256, },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
|
||||
+ { "SST25WF512", 1, 0x1000, 16, },
|
||||
+ { "SST25VF512", 0x48, 0x1000, 16, },
|
||||
+ { "SST25WF010", 2, 0x1000, 32, },
|
||||
+ { "SST25VF010", 0x49, 0x1000, 32, },
|
||||
+ { "SST25WF020", 3, 0x1000, 64, },
|
||||
+ { "SST25VF020", 0x43, 0x1000, 64, },
|
||||
+ { "SST25WF040", 4, 0x1000, 128, },
|
||||
+ { "SST25VF040", 0x44, 0x1000, 128, },
|
||||
+ { "SST25VF040B", 0x8d, 0x1000, 128, },
|
||||
+ { "SST25WF080", 5, 0x1000, 256, },
|
||||
+ { "SST25VF080B", 0x8e, 0x1000, 256, },
|
||||
+ { "SST25VF016", 0x41, 0x1000, 512, },
|
||||
+ { "SST25VF032", 0x4a, 0x1000, 1024, },
|
||||
+ { "SST25VF064", 0x4b, 0x1000, 2048, },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
|
||||
+ { "AT45DB011", 0xc, 256, 512, },
|
||||
+ { "AT45DB021", 0x14, 256, 1024, },
|
||||
+ { "AT45DB041", 0x1c, 256, 2048, },
|
||||
+ { "AT45DB081", 0x24, 256, 4096, },
|
||||
+ { "AT45DB161", 0x2c, 512, 4096, },
|
||||
+ { "AT45DB321", 0x34, 512, 8192, },
|
||||
+ { "AT45DB642", 0x3c, 1024, 8192, },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
|
||||
break;
|
||||
}
|
||||
break;
|
||||
+ case 0x13:
|
||||
+ return -ENOTSUPP;
|
||||
default:
|
||||
for (e = bcma_sflash_st_tbl; e->name; e++) {
|
||||
if (e->id == id)
|
||||
@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
- sflash->window = BCMA_SFLASH;
|
||||
+ sflash->window = BCMA_SOC_FLASH2;
|
||||
sflash->blocksize = e->blocksize;
|
||||
sflash->numblocks = e->numblocks;
|
||||
sflash->size = sflash->blocksize * sflash->numblocks;
|
||||
--- a/drivers/bcma/driver_mips.c
|
||||
+++ b/drivers/bcma/driver_mips.c
|
||||
@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc
|
||||
bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
|
||||
~(1 << irqflag));
|
||||
else
|
||||
- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
|
||||
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
|
||||
|
||||
/* assign the new one */
|
||||
if (irq == 0) {
|
||||
@@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
|
||||
struct bcma_bus *bus = mcore->core->bus;
|
||||
|
||||
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
|
||||
- return bcma_pmu_get_clockcpu(&bus->drv_cc);
|
||||
+ return bcma_pmu_get_cpu_clock(&bus->drv_cc);
|
||||
|
||||
bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
|
||||
return 0;
|
||||
@@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
|
||||
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
|
||||
{
|
||||
struct bcma_bus *bus = mcore->core->bus;
|
||||
+ struct bcma_drv_cc *cc = &bus->drv_cc;
|
||||
|
||||
- switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
|
||||
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
|
||||
case BCMA_CC_FLASHT_STSER:
|
||||
case BCMA_CC_FLASHT_ATSER:
|
||||
bcma_debug(bus, "Found serial flash\n");
|
||||
- bcma_sflash_init(&bus->drv_cc);
|
||||
+ bcma_sflash_init(cc);
|
||||
break;
|
||||
case BCMA_CC_FLASHT_PARA:
|
||||
bcma_debug(bus, "Found parallel flash\n");
|
||||
- bus->drv_cc.pflash.window = 0x1c000000;
|
||||
- bus->drv_cc.pflash.window_size = 0x02000000;
|
||||
+ cc->pflash.present = true;
|
||||
+ cc->pflash.window = BCMA_SOC_FLASH2;
|
||||
+ cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
|
||||
|
||||
- if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
|
||||
+ if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
|
||||
BCMA_CC_FLASH_CFG_DS) == 0)
|
||||
- bus->drv_cc.pflash.buswidth = 1;
|
||||
+ cc->pflash.buswidth = 1;
|
||||
else
|
||||
- bus->drv_cc.pflash.buswidth = 2;
|
||||
+ cc->pflash.buswidth = 2;
|
||||
break;
|
||||
default:
|
||||
bcma_err(bus, "Flash type not supported\n");
|
||||
}
|
||||
|
||||
- if (bus->drv_cc.core->id.rev == 38 ||
|
||||
+ if (cc->core->id.rev == 38 ||
|
||||
bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
|
||||
- if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
|
||||
+ if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
|
||||
bcma_debug(bus, "Found NAND flash\n");
|
||||
- bcma_nflash_init(&bus->drv_cc);
|
||||
+ bcma_nflash_init(cc);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
|
||||
+{
|
||||
+ struct bcma_bus *bus = mcore->core->bus;
|
||||
+
|
||||
+ if (mcore->early_setup_done)
|
||||
+ return;
|
||||
+
|
||||
+ bcma_chipco_serial_init(&bus->drv_cc);
|
||||
+ bcma_core_mips_flash_detect(mcore);
|
||||
+
|
||||
+ mcore->early_setup_done = true;
|
||||
+}
|
||||
+
|
||||
void bcma_core_mips_init(struct bcma_drv_mips *mcore)
|
||||
{
|
||||
struct bcma_bus *bus;
|
||||
struct bcma_device *core;
|
||||
bus = mcore->core->bus;
|
||||
|
||||
+ if (mcore->setup_done)
|
||||
+ return;
|
||||
+
|
||||
bcma_info(bus, "Initializing MIPS core...\n");
|
||||
|
||||
- if (!mcore->setup_done)
|
||||
- mcore->assigned_irqs = 1;
|
||||
+ bcma_core_mips_early_init(mcore);
|
||||
+
|
||||
+ mcore->assigned_irqs = 1;
|
||||
|
||||
/* Assign IRQs to all cores on the bus */
|
||||
list_for_each_entry(core, &bus->cores, list) {
|
||||
@@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv
|
||||
bcma_info(bus, "IRQ reconfiguration done\n");
|
||||
bcma_core_mips_dump_irq(bus);
|
||||
|
||||
- if (mcore->setup_done)
|
||||
- return;
|
||||
-
|
||||
- bcma_chipco_serial_init(&bus->drv_cc);
|
||||
- bcma_core_mips_flash_detect(mcore);
|
||||
mcore->setup_done = true;
|
||||
}
|
||||
--- a/drivers/bcma/driver_pci_host.c
|
||||
+++ b/drivers/bcma/driver_pci_host.c
|
||||
@@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
|
||||
chipid_top != 0x5300)
|
||||
return false;
|
||||
|
||||
- if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
||||
- bcma_info(bus, "This PCI core is disabled and not working\n");
|
||||
- return false;
|
||||
- }
|
||||
-
|
||||
bcma_core_enable(pc->core, 0);
|
||||
|
||||
return !mips_busprobe32(tmp, pc->core->io_addr);
|
||||
@@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
|
||||
|
||||
bcma_info(bus, "PCIEcore in host mode found\n");
|
||||
|
||||
+ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
||||
+ bcma_info(bus, "This PCIE core is disabled and not working\n");
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
|
||||
if (!pc_host) {
|
||||
bcma_err(bus, "can not allocate memory");
|
||||
@@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
|
||||
pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
|
||||
pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
|
||||
BCMA_SOC_PCI_MEM_SZ - 1;
|
||||
+ pc_host->io_resource.start = 0x100;
|
||||
+ pc_host->io_resource.end = 0x47F;
|
||||
pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
|
||||
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
||||
tmp | BCMA_SOC_PCI_MEM);
|
||||
@@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
|
||||
pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
|
||||
pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
|
||||
BCMA_SOC_PCI_MEM_SZ - 1;
|
||||
+ pc_host->io_resource.start = 0x480;
|
||||
+ pc_host->io_resource.end = 0x7FF;
|
||||
pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
|
||||
pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
|
||||
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
||||
@@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
|
||||
static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
- int pos;
|
||||
+ int pos, err;
|
||||
|
||||
if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
||||
/* This is not a device on the PCI-core bridge. */
|
||||
@@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
|
||||
|
||||
for (pos = 0; pos < 6; pos++) {
|
||||
res = &dev->resource[pos];
|
||||
- if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
|
||||
- pci_assign_resource(dev, pos);
|
||||
+ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
|
||||
+ err = pci_assign_resource(dev, pos);
|
||||
+ if (err)
|
||||
+ pr_err("PCI: Problem fixing up the addresses on %s\n",
|
||||
+ pci_name(dev));
|
||||
+ }
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
|
||||
--- a/drivers/bcma/host_pci.c
|
||||
+++ b/drivers/bcma/host_pci.c
|
||||
@@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
|
||||
pci_set_drvdata(dev, NULL);
|
||||
}
|
||||
|
||||
-#ifdef CONFIG_PM
|
||||
+#ifdef CONFIG_PM_SLEEP
|
||||
static int bcma_host_pci_suspend(struct device *dev)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
@@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
|
||||
bcma_host_pci_resume);
|
||||
#define BCMA_PM_OPS (&bcma_pm_ops)
|
||||
|
||||
-#else /* CONFIG_PM */
|
||||
+#else /* CONFIG_PM_SLEEP */
|
||||
|
||||
#define BCMA_PM_OPS NULL
|
||||
|
||||
-#endif /* CONFIG_PM */
|
||||
+#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
|
||||
--- a/drivers/bcma/main.c
|
||||
+++ b/drivers/bcma/main.c
|
||||
@@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(bcma_find_core);
|
||||
|
||||
+static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
|
||||
+ u8 unit)
|
||||
+{
|
||||
+ struct bcma_device *core;
|
||||
+
|
||||
+ list_for_each_entry(core, &bus->cores, list) {
|
||||
+ if (core->id.id == coreid && core->core_unit == unit)
|
||||
+ return core;
|
||||
+ }
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
static void bcma_release_core_dev(struct device *dev)
|
||||
{
|
||||
struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
||||
@@ -153,6 +165,12 @@ static int bcma_register_cores(struct bc
|
||||
}
|
||||
#endif
|
||||
|
||||
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
|
||||
+ err = bcma_chipco_watchdog_register(&bus->drv_cc);
|
||||
+ if (err)
|
||||
+ bcma_err(bus, "Error registering watchdog driver\n");
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -165,6 +183,8 @@ static void bcma_unregister_cores(struct
|
||||
if (core->dev_registered)
|
||||
device_unregister(&core->dev);
|
||||
}
|
||||
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC)
|
||||
+ platform_device_unregister(bus->drv_cc.watchdog);
|
||||
}
|
||||
|
||||
int __devinit bcma_bus_register(struct bcma_bus *bus)
|
||||
@@ -183,6 +203,20 @@ int __devinit bcma_bus_register(struct b
|
||||
return -1;
|
||||
}
|
||||
|
||||
+ /* Early init CC core */
|
||||
+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
||||
+ if (core) {
|
||||
+ bus->drv_cc.core = core;
|
||||
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
||||
+ }
|
||||
+
|
||||
+ /* Try to get SPROM */
|
||||
+ err = bcma_sprom_get(bus);
|
||||
+ if (err == -ENOENT) {
|
||||
+ bcma_err(bus, "No SPROM available\n");
|
||||
+ } else if (err)
|
||||
+ bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
||||
+
|
||||
/* Init CC core */
|
||||
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
||||
if (core) {
|
||||
@@ -198,10 +232,17 @@ int __devinit bcma_bus_register(struct b
|
||||
}
|
||||
|
||||
/* Init PCIE core */
|
||||
- core = bcma_find_core(bus, BCMA_CORE_PCIE);
|
||||
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
|
||||
if (core) {
|
||||
- bus->drv_pci.core = core;
|
||||
- bcma_core_pci_init(&bus->drv_pci);
|
||||
+ bus->drv_pci[0].core = core;
|
||||
+ bcma_core_pci_init(&bus->drv_pci[0]);
|
||||
+ }
|
||||
+
|
||||
+ /* Init PCIE core */
|
||||
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
|
||||
+ if (core) {
|
||||
+ bus->drv_pci[1].core = core;
|
||||
+ bcma_core_pci_init(&bus->drv_pci[1]);
|
||||
}
|
||||
|
||||
/* Init GBIT MAC COMMON core */
|
||||
@@ -211,13 +252,6 @@ int __devinit bcma_bus_register(struct b
|
||||
bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
|
||||
}
|
||||
|
||||
- /* Try to get SPROM */
|
||||
- err = bcma_sprom_get(bus);
|
||||
- if (err == -ENOENT) {
|
||||
- bcma_err(bus, "No SPROM available\n");
|
||||
- } else if (err)
|
||||
- bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
||||
-
|
||||
/* Register found cores */
|
||||
bcma_register_cores(bus);
|
||||
|
||||
@@ -275,18 +309,18 @@ int __init bcma_bus_early_register(struc
|
||||
return -1;
|
||||
}
|
||||
|
||||
- /* Init CC core */
|
||||
+ /* Early init CC core */
|
||||
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
||||
if (core) {
|
||||
bus->drv_cc.core = core;
|
||||
- bcma_core_chipcommon_init(&bus->drv_cc);
|
||||
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
||||
}
|
||||
|
||||
- /* Init MIPS core */
|
||||
+ /* Early init MIPS core */
|
||||
core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
||||
if (core) {
|
||||
bus->drv_mips.core = core;
|
||||
- bcma_core_mips_init(&bus->drv_mips);
|
||||
+ bcma_core_mips_early_init(&bus->drv_mips);
|
||||
}
|
||||
|
||||
bcma_info(bus, "Early bus registered\n");
|
||||
--- a/drivers/bcma/sprom.c
|
||||
+++ b/drivers/bcma/sprom.c
|
||||
@@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
||||
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
|
||||
|
||||
err = bcma_sprom_valid(sprom);
|
||||
- if (err)
|
||||
+ if (err) {
|
||||
+ bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
|
||||
+ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
|
||||
goto out;
|
||||
+ }
|
||||
|
||||
bcma_sprom_extract_r8(bus, sprom);
|
||||
|
||||
--- a/include/linux/bcma/bcma.h
|
||||
+++ b/include/linux/bcma/bcma.h
|
||||
@@ -157,6 +157,7 @@ struct bcma_host_ops {
|
||||
|
||||
/* Chip IDs of SoCs */
|
||||
#define BCMA_CHIP_ID_BCM4706 0x5300
|
||||
+#define BCMA_PKG_ID_BCM4706L 1
|
||||
#define BCMA_CHIP_ID_BCM4716 0x4716
|
||||
#define BCMA_PKG_ID_BCM4716 8
|
||||
#define BCMA_PKG_ID_BCM4717 9
|
||||
@@ -166,7 +167,11 @@ struct bcma_host_ops {
|
||||
#define BCMA_CHIP_ID_BCM4749 0x4749
|
||||
#define BCMA_CHIP_ID_BCM5356 0x5356
|
||||
#define BCMA_CHIP_ID_BCM5357 0x5357
|
||||
+#define BCMA_PKG_ID_BCM5358 9
|
||||
+#define BCMA_PKG_ID_BCM47186 10
|
||||
+#define BCMA_PKG_ID_BCM5357 11
|
||||
#define BCMA_CHIP_ID_BCM53572 53572
|
||||
+#define BCMA_PKG_ID_BCM47188 9
|
||||
|
||||
struct bcma_device {
|
||||
struct bcma_bus *bus;
|
||||
@@ -251,7 +256,7 @@ struct bcma_bus {
|
||||
u8 num;
|
||||
|
||||
struct bcma_drv_cc drv_cc;
|
||||
- struct bcma_drv_pci drv_pci;
|
||||
+ struct bcma_drv_pci drv_pci[2];
|
||||
struct bcma_drv_mips drv_mips;
|
||||
struct bcma_drv_gmac_cmn drv_gmac_cmn;
|
||||
|
||||
--- a/include/linux/bcma/bcma_driver_chipcommon.h
|
||||
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
||||
@@ -1,6 +1,8 @@
|
||||
#ifndef LINUX_BCMA_DRIVER_CC_H_
|
||||
#define LINUX_BCMA_DRIVER_CC_H_
|
||||
|
||||
+#include <linux/platform_device.h>
|
||||
+
|
||||
/** ChipCommon core registers. **/
|
||||
#define BCMA_CC_ID 0x0000
|
||||
#define BCMA_CC_ID_ID 0x0000FFFF
|
||||
@@ -510,6 +512,7 @@ struct bcma_chipcommon_pmu {
|
||||
|
||||
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
||||
struct bcma_pflash {
|
||||
+ bool present;
|
||||
u8 buswidth;
|
||||
u32 window;
|
||||
u32 window_size;
|
||||
@@ -532,6 +535,7 @@ struct mtd_info;
|
||||
|
||||
struct bcma_nflash {
|
||||
bool present;
|
||||
+ bool boot; /* This is the flash the SoC boots from */
|
||||
|
||||
struct mtd_info *mtd;
|
||||
};
|
||||
@@ -552,6 +556,7 @@ struct bcma_drv_cc {
|
||||
u32 capabilities;
|
||||
u32 capabilities_ext;
|
||||
u8 setup_done:1;
|
||||
+ u8 early_setup_done:1;
|
||||
/* Fast Powerup Delay constant */
|
||||
u16 fast_pwrup_delay;
|
||||
struct bcma_chipcommon_pmu pmu;
|
||||
@@ -567,6 +572,8 @@ struct bcma_drv_cc {
|
||||
int nr_serial_ports;
|
||||
struct bcma_serial_port serial_ports[4];
|
||||
#endif /* CONFIG_BCMA_DRIVER_MIPS */
|
||||
+ u32 ticks_per_ms;
|
||||
+ struct platform_device *watchdog;
|
||||
};
|
||||
|
||||
/* Register access */
|
||||
@@ -583,14 +590,14 @@ struct bcma_drv_cc {
|
||||
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
|
||||
|
||||
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
|
||||
+extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
|
||||
|
||||
extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
|
||||
extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
|
||||
|
||||
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
|
||||
|
||||
-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
|
||||
- u32 ticks);
|
||||
+extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
|
||||
|
||||
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
|
||||
|
||||
@@ -606,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
|
||||
|
||||
/* PMU support */
|
||||
extern void bcma_pmu_init(struct bcma_drv_cc *cc);
|
||||
+extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
|
||||
|
||||
extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
||||
u32 value);
|
||||
--- a/include/linux/bcma/bcma_driver_mips.h
|
||||
+++ b/include/linux/bcma/bcma_driver_mips.h
|
||||
@@ -35,13 +35,16 @@ struct bcma_device;
|
||||
struct bcma_drv_mips {
|
||||
struct bcma_device *core;
|
||||
u8 setup_done:1;
|
||||
+ u8 early_setup_done:1;
|
||||
unsigned int assigned_irqs;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
||||
extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
|
||||
+extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
|
||||
#else
|
||||
static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
|
||||
+static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
|
||||
#endif
|
||||
|
||||
extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
|
||||
--- a/include/linux/bcma/bcma_regs.h
|
||||
+++ b/include/linux/bcma/bcma_regs.h
|
||||
@@ -85,6 +85,9 @@
|
||||
* (2 ZettaBytes), high 32 bits
|
||||
*/
|
||||
|
||||
-#define BCMA_SFLASH 0x1c000000
|
||||
+#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
|
||||
+#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
|
||||
+#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
|
||||
+#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
|
||||
|
||||
#endif /* LINUX_BCMA_REGS_H_ */
|
||||
--- a/drivers/net/wireless/b43/main.c
|
||||
+++ b/drivers/net/wireless/b43/main.c
|
||||
@@ -4652,7 +4652,7 @@ static int b43_wireless_core_init(struct
|
||||
switch (dev->dev->bus_type) {
|
||||
#ifdef CONFIG_B43_BCMA
|
||||
case B43_BUS_BCMA:
|
||||
- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
|
||||
+ bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
|
||||
dev->dev->bdev, true);
|
||||
break;
|
||||
#endif
|
||||
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
|
||||
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
|
||||
@@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
|
||||
sii = container_of(sih, struct si_info, pub);
|
||||
|
||||
if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
|
||||
- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
|
||||
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
|
||||
}
|
||||
|
||||
/* Unconfigure and/or apply various WARs when going down */
|
||||
@@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
|
||||
sii = container_of(sih, struct si_info, pub);
|
||||
|
||||
if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
|
||||
- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
|
||||
+ bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
|
||||
}
|
||||
|
||||
/* Enable BT-COEX & Ex-PA for 4313 */
|
||||
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
|
||||
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
|
||||
@@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
|
||||
* Configure pci/pcmcia here instead of in brcms_c_attach()
|
||||
* to allow mfg hotswap: down, hotswap (chip power cycle), up.
|
||||
*/
|
||||
- bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
|
||||
+ bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
|
||||
true);
|
||||
|
||||
/*
|
Loading…
Reference in new issue