SVN-Revision: 36473master
Hauke Mehrtens
12 years ago
parent
f1e214411d
commit
1bac172c44
@ -1,18 +0,0 @@ |
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--- a/include/linux/ssb/ssb.h
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+++ b/include/linux/ssb/ssb.h
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@@ -26,6 +26,7 @@ struct ssb_sprom_core_pwr_info {
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struct ssb_sprom {
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u8 revision;
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+ u8 country_code; /* Country Code */
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u8 il0mac[6]; /* MAC address for 802.11b/g */
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u8 et0mac[6]; /* MAC address for Ethernet */
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u8 et1mac[6]; /* MAC address for 802.11a */
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@@ -36,7 +37,6 @@ struct ssb_sprom {
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u16 board_rev; /* Board revision number from SPROM. */
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u16 board_num; /* Board number from SPROM. */
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u16 board_type; /* Board type from SPROM. */
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- u8 country_code; /* Country Code */
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char alpha2[2]; /* Country Code as two chars like EU or US */
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u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
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u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
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File diff suppressed because it is too large
Load Diff
@ -1,62 +0,0 @@ |
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
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return (s8)gain;
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}
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+static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
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+{
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+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
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+ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
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+ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
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+ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
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+ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
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+ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
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+ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
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+ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
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+ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
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+ SSB_SPROM2_MAXP_A_LO_SHIFT);
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+}
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+
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static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
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{
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int i;
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@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
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SSB_SPROM1_ITSSI_A_SHIFT);
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SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
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SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
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- if (out->revision >= 2)
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- SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
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+
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SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
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SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
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@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
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out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
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SSB_SPROM1_AGAIN_A,
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SSB_SPROM1_AGAIN_A_SHIFT);
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+ if (out->revision >= 2)
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+ sprom_extract_r23(out, in);
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}
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/* Revs 4 5 and 8 have partially shared layout */
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -289,11 +289,11 @@
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#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
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#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
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#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
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-#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
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-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
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-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
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-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
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+#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
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+#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
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+#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
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#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
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#define SSB_SPROM4_AGAIN0_SHIFT 0
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File diff suppressed because it is too large
Load Diff
@ -1,140 +0,0 @@ |
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
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return value;
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}
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-static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
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+u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
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{
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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return bcma_pmu_get_alp_clock(cc);
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return 20000000;
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}
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+EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
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static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
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{
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@@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
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return res;
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}
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+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
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u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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@@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
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return res;
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}
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+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
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/*
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* If the bit is set to 0, chipcommon controlls this GPIO,
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--- a/drivers/bcma/driver_chipcommon_pmu.c
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+++ b/drivers/bcma/driver_chipcommon_pmu.c
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@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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+ case BCMA_CHIP_ID_BCM4313:
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+ case BCMA_CHIP_ID_BCM43224:
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+ case BCMA_CHIP_ID_BCM43225:
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+ case BCMA_CHIP_ID_BCM43227:
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+ case BCMA_CHIP_ID_BCM43228:
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+ case BCMA_CHIP_ID_BCM4331:
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+ case BCMA_CHIP_ID_BCM43421:
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+ case BCMA_CHIP_ID_BCM43428:
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+ case BCMA_CHIP_ID_BCM43431:
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case BCMA_CHIP_ID_BCM4716:
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- case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM47162:
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- case BCMA_CHIP_ID_BCM4313:
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- case BCMA_CHIP_ID_BCM5357:
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+ case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM4749:
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+ case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM53572:
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+ case BCMA_CHIP_ID_BCM6362:
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/* always 20Mhz */
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return 20000 * 1000;
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- case BCMA_CHIP_ID_BCM5356:
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case BCMA_CHIP_ID_BCM4706:
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+ case BCMA_CHIP_ID_BCM5356:
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/* always 25Mhz */
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return 25000 * 1000;
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+ case BCMA_CHIP_ID_BCM43460:
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+ case BCMA_CHIP_ID_BCM4352:
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+ case BCMA_CHIP_ID_BCM4360:
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+ if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
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+ return 40000 * 1000;
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+ else
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+ return 20000 * 1000;
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default:
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bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
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@@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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case BCMA_CHIP_ID_BCM4331:
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@@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
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0x03000a08);
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}
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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case BCMA_CHIP_ID_BCM43224:
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@@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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}
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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case BCMA_CHIP_ID_BCM4716:
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@@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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0x88888815);
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}
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- tmp = 3 << 9;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
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break;
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case BCMA_CHIP_ID_BCM43227:
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@@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
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0x88888815);
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}
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- tmp = 1 << 10;
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+ tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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default:
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bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -104,6 +104,7 @@
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#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
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#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
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#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
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+#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
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#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
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#define BCMA_CC_JCMD_START 0x80000000
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#define BCMA_CC_JCMD_BUSY 0x80000000
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@@ -607,6 +608,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
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extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
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+extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
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+
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
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