Based on a patch by Layne Edwards <ledwards@astrumtech.net> SVN-Revision: 27997master
parent
0ca16a4600
commit
169d68c98c
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config DWC_OTG |
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tristate "Ralink RT305X DWC_OTG support" |
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depends on SOC_RT305X |
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---help--- |
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This driver supports Ralink DWC_OTG |
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choice |
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prompt "USB Operation Mode" |
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depends on DWC_OTG |
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default DWC_OTG_HOST_ONLY |
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config DWC_OTG_HOST_ONLY |
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bool "HOST ONLY MODE" |
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depends on DWC_OTG |
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config DWC_OTG_DEVICE_ONLY |
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bool "DEVICE ONLY MODE" |
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depends on DWC_OTG |
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endchoice |
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config DWC_OTG_DEBUG |
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bool "Enable debug mode" |
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depends on DWC_OTG |
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#
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# Makefile for DWC_otg Highspeed USB controller driver
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#
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ifeq ($(CONFIG_DWC_OTG_DEBUG),y) |
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EXTRA_CFLAGS += -DDEBUG
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endif |
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# Use one of the following flags to compile the software in host-only or
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# device-only mode.
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ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y) |
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EXTRA_CFLAGS += -DDWC_HOST_ONLY
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EXTRA_CFLAGS += -DDWC_EN_ISOC
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endif |
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ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y) |
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EXTRA_CFLAGS += -DDWC_DEVICE_ONLY
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endif |
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obj-$(CONFIG_DWC_OTG) := dwc_otg.o
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dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
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dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
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dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
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dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
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Load Diff
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/* ==========================================================================
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* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
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* $Revision: 1.2 $ |
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* $Date: 2008-11-21 05:39:15 $ |
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* $Change: 1064918 $ |
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* |
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* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
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* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
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* otherwise expressly agreed to in writing between Synopsys and you. |
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* |
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* The Software IS NOT an item of Licensed Software or Licensed Product under |
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* any End User Software License Agreement or Agreement for Licensed Product |
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* with Synopsys or any supplement thereto. You are permitted to use and |
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* redistribute this Software in source and binary forms, with or without |
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* modification, provided that redistributions of source code must retain this |
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* notice. You may not view, use, disclose, copy or distribute this file or |
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* any information contained herein except pursuant to this license grant from |
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* Synopsys. If you do not agree with this notice, including the disclaimer |
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* below, then you are not authorized to use the Software. |
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* |
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
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* DAMAGE. |
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* ========================================================================== */ |
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|
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/** @file
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* |
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* The diagnostic interface will provide access to the controller for |
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* bringing up the hardware and testing. The Linux driver attributes |
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* feature will be used to provide the Linux Diagnostic |
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* Interface. These attributes are accessed through sysfs. |
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*/ |
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/** @page "Linux Module Attributes"
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* |
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* The Linux module attributes feature is used to provide the Linux |
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* Diagnostic Interface. These attributes are accessed through sysfs. |
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* The diagnostic interface will provide access to the controller for |
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* bringing up the hardware and testing. |
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The following table shows the attributes. |
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<table> |
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<tr> |
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<td><b> Name</b></td> |
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<td><b> Description</b></td> |
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<td><b> Access</b></td> |
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</tr> |
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<tr> |
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<td> mode </td> |
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<td> Returns the current mode: 0 for device mode, 1 for host mode</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> hnpcapable </td> |
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<td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. |
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Read returns the current value.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> srpcapable </td> |
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<td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. |
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Read returns the current value.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> hnp </td> |
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<td> Initiates the Host Negotiation Protocol. Read returns the status.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> srp </td> |
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<td> Initiates the Session Request Protocol. Read returns the status.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> buspower </td> |
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<td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> bussuspend </td> |
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<td> Suspends the USB bus.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> busconnected </td> |
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<td> Gets the connection status of the bus</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> gotgctl </td> |
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<td> Gets or sets the Core Control Status Register.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> gusbcfg </td> |
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<td> Gets or sets the Core USB Configuration Register</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> grxfsiz </td> |
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<td> Gets or sets the Receive FIFO Size Register</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> gnptxfsiz </td> |
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<td> Gets or sets the non-periodic Transmit Size Register</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> gpvndctl </td> |
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<td> Gets or sets the PHY Vendor Control Register</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> ggpio </td> |
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<td> Gets the value in the lower 16-bits of the General Purpose IO Register |
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or sets the upper 16 bits.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> guid </td> |
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<td> Gets or sets the value of the User ID Register</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> gsnpsid </td> |
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<td> Gets the value of the Synopsys ID Regester</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> devspeed </td> |
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<td> Gets or sets the device speed setting in the DCFG register</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> enumspeed </td> |
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<td> Gets the device enumeration Speed.</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> hptxfsiz </td> |
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<td> Gets the value of the Host Periodic Transmit FIFO</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> hprt0 </td> |
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<td> Gets or sets the value in the Host Port Control and Status Register</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> regoffset </td> |
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<td> Sets the register offset for the next Register Access</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> regvalue </td> |
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<td> Gets or sets the value of the register at the offset in the regoffset attribute.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> remote_wakeup </td> |
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<td> On read, shows the status of Remote Wakeup. On write, initiates a remote |
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wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote |
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Wakeup signalling bit in the Device Control Register is set for 1 |
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milli-second.</td> |
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<td> Read/Write</td> |
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</tr> |
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<tr> |
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<td> regdump </td> |
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<td> Dumps the contents of core registers.</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> spramdump </td> |
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<td> Dumps the contents of core registers.</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> hcddump </td> |
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<td> Dumps the current HCD state.</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> hcd_frrem </td> |
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<td> Shows the average value of the Frame Remaining |
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field in the Host Frame Number/Frame Remaining register when an SOF interrupt |
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occurs. This can be used to determine the average interrupt latency. Also |
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shows the average Frame Remaining value for start_transfer and the "a" and |
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"b" sample points. The "a" and "b" sample points may be used during debugging |
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bto determine how long it takes to execute a section of the HCD code.</td> |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> rd_reg_test </td> |
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<td> Displays the time required to read the GNPTXFSIZ register many times |
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(the output shows the number of times the register is read). |
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<td> Read</td> |
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</tr> |
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<tr> |
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<td> wr_reg_test </td> |
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<td> Displays the time required to write the GNPTXFSIZ register many times |
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(the output shows the number of times the register is written). |
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<td> Read</td> |
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</tr> |
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</table> |
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Example usage: |
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To get the current mode: |
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cat /sys/devices/lm0/mode |
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To power down the USB: |
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echo 0 > /sys/devices/lm0/buspower |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/init.h> |
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#include <linux/device.h> |
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#include <linux/errno.h> |
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#include <linux/types.h> |
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#include <linux/stat.h> /* permission constants */ |
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#include <linux/version.h> |
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#include <asm/io.h> |
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#include "linux/dwc_otg_plat.h" |
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#include "dwc_otg_attr.h" |
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#include "dwc_otg_driver.h" |
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#include "dwc_otg_pcd.h" |
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#include "dwc_otg_hcd.h" |
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
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/*
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* MACROs for defining sysfs attribute |
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*/ |
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#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ |
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static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
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uint32_t val; \
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val = dwc_read_reg32 (_addr_); \
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val = (val & (_mask_)) >> _shift_; \
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return sprintf (buf, "%s = 0x%x\n", _string_, val); \
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} |
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#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ |
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static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
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const char *buf, size_t count) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
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uint32_t set = simple_strtoul(buf, NULL, 16); \
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uint32_t clear = set; \
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clear = ((~clear) << _shift_) & _mask_; \
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set = (set << _shift_) & _mask_; \
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dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
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dwc_modify_reg32(_addr_, clear, set); \
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return count; \
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} |
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/*
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* MACROs for defining sysfs attribute for 32-bit registers |
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*/ |
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#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ |
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static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
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uint32_t val; \
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val = dwc_read_reg32 (_addr_); \
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return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
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} |
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#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ |
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static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
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const char *buf, size_t count) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
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uint32_t val = simple_strtoul(buf, NULL, 16); \
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dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
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dwc_write_reg32(_addr_, val); \
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return count; \
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} |
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#else |
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/*
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* MACROs for defining sysfs attribute |
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*/ |
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#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ |
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static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
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uint32_t val; \
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val = dwc_read_reg32 (_addr_); \
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val = (val & (_mask_)) >> _shift_; \
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return sprintf (buf, "%s = 0x%x\n", _string_, val); \
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} |
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#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ |
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static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
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uint32_t set = simple_strtoul(buf, NULL, 16); \
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uint32_t clear = set; \
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clear = ((~clear) << _shift_) & _mask_; \
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set = (set << _shift_) & _mask_; \
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dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
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dwc_modify_reg32(_addr_, clear, set); \
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return count; \
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} |
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/*
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* MACROs for defining sysfs attribute for 32-bit registers |
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*/ |
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#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ |
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static ssize_t _otg_attr_name_##_show (struct device *_dev, char *buf) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
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uint32_t val; \
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val = dwc_read_reg32 (_addr_); \
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return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
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} |
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#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ |
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static ssize_t _otg_attr_name_##_store (struct device *_dev, const char *buf, size_t count) \
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{ \
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
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uint32_t val = simple_strtoul(buf, NULL, 16); \
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dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
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dwc_write_reg32(_addr_, val); \
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return count; \
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} |
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#endif |
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#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ |
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DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
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DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
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DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); |
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#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ |
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DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
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DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); |
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#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ |
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DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
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DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
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DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); |
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#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ |
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DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
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DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); |
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/** @name Functions for Show/Store of Attributes */ |
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/**@{*/ |
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/**
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* Show the register offset of the Register Access. |
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*/ |
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static ssize_t regoffset_show( struct device *_dev, |
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
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struct device_attribute *attr, |
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#endif |
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char *buf) |
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{ |
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dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
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return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset); |
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} |
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/**
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* Set the register offset for the next Register Access Read/Write |
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*/ |
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static ssize_t regoffset_store( struct device *_dev, |
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
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struct device_attribute *attr, |
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#endif |
||||
const char *buf, |
||||
size_t count ) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
uint32_t offset = simple_strtoul(buf, NULL, 16); |
||||
//dev_dbg(_dev, "Offset=0x%08x\n", offset);
|
||||
if (offset < 0x00040000 ) { |
||||
otg_dev->reg_offset = offset; |
||||
} |
||||
else { |
||||
dev_err( _dev, "invalid offset\n" ); |
||||
} |
||||
|
||||
return count; |
||||
} |
||||
DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, (void *)regoffset_show, regoffset_store); |
||||
|
||||
|
||||
/**
|
||||
* Show the value of the register at the offset in the reg_offset |
||||
* attribute. |
||||
*/ |
||||
static ssize_t regvalue_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
uint32_t val; |
||||
volatile uint32_t *addr; |
||||
|
||||
if (otg_dev->reg_offset != 0xFFFFFFFF && |
||||
0 != otg_dev->base) { |
||||
/* Calculate the address */ |
||||
addr = (uint32_t*)(otg_dev->reg_offset + |
||||
(uint8_t*)otg_dev->base); |
||||
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
|
||||
val = dwc_read_reg32( addr ); |
||||
return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1, |
||||
"Reg@0x%06x = 0x%08x\n", |
||||
otg_dev->reg_offset, val); |
||||
} |
||||
else { |
||||
dev_err(_dev, "Invalid offset (0x%0x)\n", |
||||
otg_dev->reg_offset); |
||||
return sprintf(buf, "invalid offset\n" ); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* Store the value in the register at the offset in the reg_offset |
||||
* attribute. |
||||
* |
||||
*/ |
||||
static ssize_t regvalue_store( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
const char *buf, |
||||
size_t count ) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
volatile uint32_t * addr; |
||||
uint32_t val = simple_strtoul(buf, NULL, 16); |
||||
//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
|
||||
if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { |
||||
/* Calculate the address */ |
||||
addr = (uint32_t*)(otg_dev->reg_offset + |
||||
(uint8_t*)otg_dev->base); |
||||
//dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
|
||||
dwc_write_reg32( addr, val ); |
||||
} |
||||
else { |
||||
dev_err(_dev, "Invalid Register Offset (0x%08x)\n", |
||||
otg_dev->reg_offset); |
||||
} |
||||
return count; |
||||
} |
||||
DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store); |
||||
|
||||
/*
|
||||
* Attributes |
||||
*/ |
||||
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode"); |
||||
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode"); |
||||
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode"); |
||||
|
||||
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
|
||||
//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
|
||||
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected"); |
||||
|
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID"); |
||||
DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed"); |
||||
DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed"); |
||||
|
||||
DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ"); |
||||
DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0"); |
||||
|
||||
|
||||
/**
|
||||
* @todo Add code to initiate the HNP. |
||||
*/ |
||||
/**
|
||||
* Show the HNP status bit |
||||
*/ |
||||
static ssize_t hnp_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
gotgctl_data_t val; |
||||
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); |
||||
return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs); |
||||
} |
||||
|
||||
/**
|
||||
* Set the HNP Request bit |
||||
*/ |
||||
static ssize_t hnp_store( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
const char *buf, |
||||
size_t count ) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
uint32_t in = simple_strtoul(buf, NULL, 16); |
||||
uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl); |
||||
gotgctl_data_t mem; |
||||
mem.d32 = dwc_read_reg32(addr); |
||||
mem.b.hnpreq = in; |
||||
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); |
||||
dwc_write_reg32(addr, mem.d32); |
||||
return count; |
||||
} |
||||
DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); |
||||
|
||||
/**
|
||||
* @todo Add code to initiate the SRP. |
||||
*/ |
||||
/**
|
||||
* Show the SRP status bit |
||||
*/ |
||||
static ssize_t srp_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
#ifndef DWC_HOST_ONLY |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
gotgctl_data_t val; |
||||
val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); |
||||
return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs); |
||||
#else |
||||
return sprintf(buf, "Host Only Mode!\n"); |
||||
#endif |
||||
} |
||||
|
||||
|
||||
|
||||
/**
|
||||
* Set the SRP Request bit |
||||
*/ |
||||
static ssize_t srp_store( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
const char *buf, |
||||
size_t count ) |
||||
{ |
||||
#ifndef DWC_HOST_ONLY |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
dwc_otg_pcd_initiate_srp(otg_dev->pcd); |
||||
#endif |
||||
return count; |
||||
} |
||||
DEVICE_ATTR(srp, 0644, srp_show, srp_store); |
||||
|
||||
/**
|
||||
* @todo Need to do more for power on/off? |
||||
*/ |
||||
/**
|
||||
* Show the Bus Power status |
||||
*/ |
||||
static ssize_t buspower_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
hprt0_data_t val; |
||||
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); |
||||
return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* Set the Bus Power status |
||||
*/ |
||||
static ssize_t buspower_store( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
const char *buf, |
||||
size_t count ) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
uint32_t on = simple_strtoul(buf, NULL, 16); |
||||
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; |
||||
hprt0_data_t mem; |
||||
|
||||
mem.d32 = dwc_read_reg32(addr); |
||||
mem.b.prtpwr = on; |
||||
|
||||
//dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
|
||||
dwc_write_reg32(addr, mem.d32); |
||||
|
||||
return count; |
||||
} |
||||
DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); |
||||
|
||||
/**
|
||||
* @todo Need to do more for suspend? |
||||
*/ |
||||
/**
|
||||
* Show the Bus Suspend status |
||||
*/ |
||||
static ssize_t bussuspend_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
hprt0_data_t val; |
||||
val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); |
||||
return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); |
||||
} |
||||
|
||||
/**
|
||||
* Set the Bus Suspend status |
||||
*/ |
||||
static ssize_t bussuspend_store( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
const char *buf, |
||||
size_t count ) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
uint32_t in = simple_strtoul(buf, NULL, 16); |
||||
uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; |
||||
hprt0_data_t mem; |
||||
mem.d32 = dwc_read_reg32(addr); |
||||
mem.b.prtsusp = in; |
||||
dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); |
||||
dwc_write_reg32(addr, mem.d32); |
||||
return count; |
||||
} |
||||
DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); |
||||
|
||||
/**
|
||||
* Show the status of Remote Wakeup. |
||||
*/ |
||||
static ssize_t remote_wakeup_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
#ifndef DWC_HOST_ONLY |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
dctl_data_t val; |
||||
val.d32 = |
||||
dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl); |
||||
return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", |
||||
val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable); |
||||
#else |
||||
return sprintf(buf, "Host Only Mode!\n"); |
||||
#endif |
||||
} |
||||
/**
|
||||
* Initiate a remote wakeup of the host. The Device control register |
||||
* Remote Wakeup Signal bit is written if the PCD Remote wakeup enable |
||||
* flag is set. |
||||
* |
||||
*/ |
||||
static ssize_t remote_wakeup_store( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
const char *buf, |
||||
size_t count ) |
||||
{ |
||||
#ifndef DWC_HOST_ONLY |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
uint32_t val = simple_strtoul(buf, NULL, 16); |
||||
if (val&1) { |
||||
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); |
||||
} |
||||
else { |
||||
dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); |
||||
} |
||||
#endif |
||||
return count; |
||||
} |
||||
DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show, |
||||
remote_wakeup_store); |
||||
|
||||
/**
|
||||
* Dump global registers and either host or device registers (depending on the |
||||
* current mode of the core). |
||||
*/ |
||||
static ssize_t regdump_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
dwc_otg_dump_global_registers( otg_dev->core_if); |
||||
if (dwc_otg_is_host_mode(otg_dev->core_if)) { |
||||
dwc_otg_dump_host_registers( otg_dev->core_if); |
||||
} else { |
||||
dwc_otg_dump_dev_registers( otg_dev->core_if); |
||||
|
||||
} |
||||
return sprintf( buf, "Register Dump\n" ); |
||||
} |
||||
|
||||
DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0); |
||||
|
||||
/**
|
||||
* Dump global registers and either host or device registers (depending on the |
||||
* current mode of the core). |
||||
*/ |
||||
static ssize_t spramdump_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
dwc_otg_dump_spram( otg_dev->core_if); |
||||
|
||||
return sprintf( buf, "SPRAM Dump\n" ); |
||||
} |
||||
|
||||
DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0); |
||||
|
||||
/**
|
||||
* Dump the current hcd state. |
||||
*/ |
||||
static ssize_t hcddump_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
#ifndef DWC_DEVICE_ONLY |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
dwc_otg_hcd_dump_state(otg_dev->hcd); |
||||
#endif |
||||
return sprintf( buf, "HCD Dump\n" ); |
||||
} |
||||
|
||||
DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0); |
||||
|
||||
/**
|
||||
* Dump the average frame remaining at SOF. This can be used to |
||||
* determine average interrupt latency. Frame remaining is also shown for |
||||
* start transfer and two additional sample points. |
||||
*/ |
||||
static ssize_t hcd_frrem_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
#ifndef DWC_DEVICE_ONLY |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
dwc_otg_hcd_dump_frrem(otg_dev->hcd); |
||||
#endif |
||||
return sprintf( buf, "HCD Dump Frame Remaining\n" ); |
||||
} |
||||
|
||||
DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0); |
||||
|
||||
/**
|
||||
* Displays the time required to read the GNPTXFSIZ register many times (the |
||||
* output shows the number of times the register is read). |
||||
*/ |
||||
#define RW_REG_COUNT 10000000 |
||||
#define MSEC_PER_JIFFIE 1000/HZ |
||||
static ssize_t rd_reg_test_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
int i; |
||||
int time; |
||||
int start_jiffies; |
||||
|
||||
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", |
||||
HZ, MSEC_PER_JIFFIE, loops_per_jiffy); |
||||
start_jiffies = jiffies; |
||||
for (i = 0; i < RW_REG_COUNT; i++) { |
||||
dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); |
||||
} |
||||
time = jiffies - start_jiffies; |
||||
return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", |
||||
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time ); |
||||
} |
||||
|
||||
DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0); |
||||
|
||||
/**
|
||||
* Displays the time required to write the GNPTXFSIZ register many times (the |
||||
* output shows the number of times the register is written). |
||||
*/ |
||||
static ssize_t wr_reg_test_show( struct device *_dev, |
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) |
||||
struct device_attribute *attr, |
||||
#endif |
||||
char *buf) |
||||
{ |
||||
dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); |
||||
|
||||
uint32_t reg_val; |
||||
int i; |
||||
int time; |
||||
int start_jiffies; |
||||
|
||||
printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", |
||||
HZ, MSEC_PER_JIFFIE, loops_per_jiffy); |
||||
reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); |
||||
start_jiffies = jiffies; |
||||
for (i = 0; i < RW_REG_COUNT; i++) { |
||||
dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val); |
||||
} |
||||
time = jiffies - start_jiffies; |
||||
return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", |
||||
RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); |
||||
} |
||||
|
||||
DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0); |
||||
/**@}*/ |
||||
|
||||
/**
|
||||
* Create the device files |
||||
*/ |
||||
void dwc_otg_attr_create (struct device *dev) |
||||
{ |
||||
int error; |
||||
|
||||
error = device_create_file(dev, &dev_attr_regoffset); |
||||
error = device_create_file(dev, &dev_attr_regvalue); |
||||
error = device_create_file(dev, &dev_attr_mode); |
||||
error = device_create_file(dev, &dev_attr_hnpcapable); |
||||
error = device_create_file(dev, &dev_attr_srpcapable); |
||||
error = device_create_file(dev, &dev_attr_hnp); |
||||
error = device_create_file(dev, &dev_attr_srp); |
||||
error = device_create_file(dev, &dev_attr_buspower); |
||||
error = device_create_file(dev, &dev_attr_bussuspend); |
||||
error = device_create_file(dev, &dev_attr_busconnected); |
||||
error = device_create_file(dev, &dev_attr_gotgctl); |
||||
error = device_create_file(dev, &dev_attr_gusbcfg); |
||||
error = device_create_file(dev, &dev_attr_grxfsiz); |
||||
error = device_create_file(dev, &dev_attr_gnptxfsiz); |
||||
error = device_create_file(dev, &dev_attr_gpvndctl); |
||||
error = device_create_file(dev, &dev_attr_ggpio); |
||||
error = device_create_file(dev, &dev_attr_guid); |
||||
error = device_create_file(dev, &dev_attr_gsnpsid); |
||||
error = device_create_file(dev, &dev_attr_devspeed); |
||||
error = device_create_file(dev, &dev_attr_enumspeed); |
||||
error = device_create_file(dev, &dev_attr_hptxfsiz); |
||||
error = device_create_file(dev, &dev_attr_hprt0); |
||||
error = device_create_file(dev, &dev_attr_remote_wakeup); |
||||
error = device_create_file(dev, &dev_attr_regdump); |
||||
error = device_create_file(dev, &dev_attr_spramdump); |
||||
error = device_create_file(dev, &dev_attr_hcddump); |
||||
error = device_create_file(dev, &dev_attr_hcd_frrem); |
||||
error = device_create_file(dev, &dev_attr_rd_reg_test); |
||||
error = device_create_file(dev, &dev_attr_wr_reg_test); |
||||
} |
||||
|
||||
/**
|
||||
* Remove the device files |
||||
*/ |
||||
void dwc_otg_attr_remove (struct device *dev) |
||||
{ |
||||
device_remove_file(dev, &dev_attr_regoffset); |
||||
device_remove_file(dev, &dev_attr_regvalue); |
||||
device_remove_file(dev, &dev_attr_mode); |
||||
device_remove_file(dev, &dev_attr_hnpcapable); |
||||
device_remove_file(dev, &dev_attr_srpcapable); |
||||
device_remove_file(dev, &dev_attr_hnp); |
||||
device_remove_file(dev, &dev_attr_srp); |
||||
device_remove_file(dev, &dev_attr_buspower); |
||||
device_remove_file(dev, &dev_attr_bussuspend); |
||||
device_remove_file(dev, &dev_attr_busconnected); |
||||
device_remove_file(dev, &dev_attr_gotgctl); |
||||
device_remove_file(dev, &dev_attr_gusbcfg); |
||||
device_remove_file(dev, &dev_attr_grxfsiz); |
||||
device_remove_file(dev, &dev_attr_gnptxfsiz); |
||||
device_remove_file(dev, &dev_attr_gpvndctl); |
||||
device_remove_file(dev, &dev_attr_ggpio); |
||||
device_remove_file(dev, &dev_attr_guid); |
||||
device_remove_file(dev, &dev_attr_gsnpsid); |
||||
device_remove_file(dev, &dev_attr_devspeed); |
||||
device_remove_file(dev, &dev_attr_enumspeed); |
||||
device_remove_file(dev, &dev_attr_hptxfsiz); |
||||
device_remove_file(dev, &dev_attr_hprt0); |
||||
device_remove_file(dev, &dev_attr_remote_wakeup); |
||||
device_remove_file(dev, &dev_attr_regdump); |
||||
device_remove_file(dev, &dev_attr_spramdump); |
||||
device_remove_file(dev, &dev_attr_hcddump); |
||||
device_remove_file(dev, &dev_attr_hcd_frrem); |
||||
device_remove_file(dev, &dev_attr_rd_reg_test); |
||||
device_remove_file(dev, &dev_attr_wr_reg_test); |
||||
} |
@ -0,0 +1,67 @@ |
||||
/* ==========================================================================
|
||||
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
|
||||
* $Revision: 1.2 $ |
||||
* $Date: 2008-11-21 05:39:15 $ |
||||
* $Change: 477051 $ |
||||
* |
||||
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
||||
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
||||
* otherwise expressly agreed to in writing between Synopsys and you. |
||||
* |
||||
* The Software IS NOT an item of Licensed Software or Licensed Product under |
||||
* any End User Software License Agreement or Agreement for Licensed Product |
||||
* with Synopsys or any supplement thereto. You are permitted to use and |
||||
* redistribute this Software in source and binary forms, with or without |
||||
* modification, provided that redistributions of source code must retain this |
||||
* notice. You may not view, use, disclose, copy or distribute this file or |
||||
* any information contained herein except pursuant to this license grant from |
||||
* Synopsys. If you do not agree with this notice, including the disclaimer |
||||
* below, then you are not authorized to use the Software. |
||||
* |
||||
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
||||
* DAMAGE. |
||||
* ========================================================================== */ |
||||
|
||||
#if !defined(__DWC_OTG_ATTR_H__) |
||||
#define __DWC_OTG_ATTR_H__ |
||||
|
||||
/** @file
|
||||
* This file contains the interface to the Linux device attributes. |
||||
*/ |
||||
extern struct device_attribute dev_attr_regoffset; |
||||
extern struct device_attribute dev_attr_regvalue; |
||||
|
||||
extern struct device_attribute dev_attr_mode; |
||||
extern struct device_attribute dev_attr_hnpcapable; |
||||
extern struct device_attribute dev_attr_srpcapable; |
||||
extern struct device_attribute dev_attr_hnp; |
||||
extern struct device_attribute dev_attr_srp; |
||||
extern struct device_attribute dev_attr_buspower; |
||||
extern struct device_attribute dev_attr_bussuspend; |
||||
extern struct device_attribute dev_attr_busconnected; |
||||
extern struct device_attribute dev_attr_gotgctl; |
||||
extern struct device_attribute dev_attr_gusbcfg; |
||||
extern struct device_attribute dev_attr_grxfsiz; |
||||
extern struct device_attribute dev_attr_gnptxfsiz; |
||||
extern struct device_attribute dev_attr_gpvndctl; |
||||
extern struct device_attribute dev_attr_ggpio; |
||||
extern struct device_attribute dev_attr_guid; |
||||
extern struct device_attribute dev_attr_gsnpsid; |
||||
extern struct device_attribute dev_attr_devspeed; |
||||
extern struct device_attribute dev_attr_enumspeed; |
||||
extern struct device_attribute dev_attr_hptxfsiz; |
||||
extern struct device_attribute dev_attr_hprt0; |
||||
|
||||
void dwc_otg_attr_create (struct device *dev); |
||||
void dwc_otg_attr_remove (struct device *dev); |
||||
|
||||
#endif |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,750 @@ |
||||
/* ==========================================================================
|
||||
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
|
||||
* $Revision: 1.2 $ |
||||
* $Date: 2008-11-21 05:39:15 $ |
||||
* $Change: 1065567 $ |
||||
* |
||||
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
||||
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
||||
* otherwise expressly agreed to in writing between Synopsys and you. |
||||
* |
||||
* The Software IS NOT an item of Licensed Software or Licensed Product under |
||||
* any End User Software License Agreement or Agreement for Licensed Product |
||||
* with Synopsys or any supplement thereto. You are permitted to use and |
||||
* redistribute this Software in source and binary forms, with or without |
||||
* modification, provided that redistributions of source code must retain this |
||||
* notice. You may not view, use, disclose, copy or distribute this file or |
||||
* any information contained herein except pursuant to this license grant from |
||||
* Synopsys. If you do not agree with this notice, including the disclaimer |
||||
* below, then you are not authorized to use the Software. |
||||
* |
||||
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
||||
* DAMAGE. |
||||
* ========================================================================== */ |
||||
|
||||
/** @file
|
||||
* |
||||
* The Core Interface Layer provides basic services for accessing and |
||||
* managing the DWC_otg hardware. These services are used by both the |
||||
* Host Controller Driver and the Peripheral Controller Driver. |
||||
* |
||||
* This file contains the Common Interrupt handlers. |
||||
*/ |
||||
#include "linux/dwc_otg_plat.h" |
||||
#include "dwc_otg_regs.h" |
||||
#include "dwc_otg_cil.h" |
||||
|
||||
#ifdef DEBUG |
||||
inline const char *op_state_str(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
return (core_if->op_state==A_HOST?"a_host": |
||||
(core_if->op_state==A_SUSPEND?"a_suspend": |
||||
(core_if->op_state==A_PERIPHERAL?"a_peripheral": |
||||
(core_if->op_state==B_PERIPHERAL?"b_peripheral": |
||||
(core_if->op_state==B_HOST?"b_host": |
||||
"unknown"))))); |
||||
} |
||||
#endif |
||||
|
||||
/** This function will log a debug message
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if) |
||||
{ |
||||
gintsts_data_t gintsts; |
||||
DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", |
||||
dwc_otg_mode(core_if) ? "Host" : "Device"); |
||||
|
||||
/* Clear interrupt */ |
||||
gintsts.d32 = 0; |
||||
gintsts.b.modemismatch = 1; |
||||
dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); |
||||
return 1; |
||||
} |
||||
|
||||
/** Start the HCD. Helper function for using the HCD callbacks.
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void hcd_start(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->hcd_cb && core_if->hcd_cb->start) { |
||||
core_if->hcd_cb->start(core_if->hcd_cb->p); |
||||
} |
||||
} |
||||
/** Stop the HCD. Helper function for using the HCD callbacks.
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void hcd_stop(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->hcd_cb && core_if->hcd_cb->stop) { |
||||
core_if->hcd_cb->stop(core_if->hcd_cb->p); |
||||
} |
||||
} |
||||
/** Disconnect the HCD. Helper function for using the HCD callbacks.
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void hcd_disconnect(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { |
||||
core_if->hcd_cb->disconnect(core_if->hcd_cb->p); |
||||
} |
||||
} |
||||
/** Inform the HCD the a New Session has begun. Helper function for
|
||||
* using the HCD callbacks. |
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void hcd_session_start(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->hcd_cb && core_if->hcd_cb->session_start) { |
||||
core_if->hcd_cb->session_start(core_if->hcd_cb->p); |
||||
} |
||||
} |
||||
|
||||
/** Start the PCD. Helper function for using the PCD callbacks.
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void pcd_start(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->pcd_cb && core_if->pcd_cb->start) { |
||||
core_if->pcd_cb->start(core_if->pcd_cb->p); |
||||
} |
||||
} |
||||
/** Stop the PCD. Helper function for using the PCD callbacks.
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void pcd_stop(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->pcd_cb && core_if->pcd_cb->stop) { |
||||
core_if->pcd_cb->stop(core_if->pcd_cb->p); |
||||
} |
||||
} |
||||
/** Suspend the PCD. Helper function for using the PCD callbacks.
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void pcd_suspend(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->pcd_cb && core_if->pcd_cb->suspend) { |
||||
core_if->pcd_cb->suspend(core_if->pcd_cb->p); |
||||
} |
||||
} |
||||
/** Resume the PCD. Helper function for using the PCD callbacks.
|
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
static inline void pcd_resume(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { |
||||
core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* This function handles the OTG Interrupts. It reads the OTG |
||||
* Interrupt Register (GOTGINT) to determine what interrupt has |
||||
* occurred. |
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
dwc_otg_core_global_regs_t *global_regs = |
||||
core_if->core_global_regs; |
||||
gotgint_data_t gotgint; |
||||
gotgctl_data_t gotgctl; |
||||
gintmsk_data_t gintmsk; |
||||
|
||||
gotgint.d32 = dwc_read_reg32(&global_regs->gotgint); |
||||
gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); |
||||
DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32); |
||||
|
||||
if (gotgint.b.sesenddet) { |
||||
DWC_DEBUGPL(DBG_ANY, "OTG Interrupt: " |
||||
"Session End Detected++ (%s)\n", |
||||
op_state_str(core_if)); |
||||
gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); |
||||
|
||||
if (core_if->op_state == B_HOST) { |
||||
pcd_start(core_if); |
||||
core_if->op_state = B_PERIPHERAL; |
||||
} else { |
||||
/* If not B_HOST and Device HNP still set. HNP
|
||||
* Did not succeed!*/ |
||||
if (gotgctl.b.devhnpen) { |
||||
DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); |
||||
DWC_ERROR("Device Not Connected/Responding!\n"); |
||||
} |
||||
|
||||
/* If Session End Detected the B-Cable has
|
||||
* been disconnected. */ |
||||
/* Reset PCD and Gadget driver to a
|
||||
* clean state. */ |
||||
pcd_stop(core_if); |
||||
} |
||||
gotgctl.d32 = 0; |
||||
gotgctl.b.devhnpen = 1; |
||||
dwc_modify_reg32(&global_regs->gotgctl, |
||||
gotgctl.d32, 0); |
||||
} |
||||
if (gotgint.b.sesreqsucstschng) { |
||||
DWC_DEBUGPL(DBG_ANY, " OTG Interrupt: " |
||||
"Session Reqeust Success Status Change++\n"); |
||||
gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); |
||||
if (gotgctl.b.sesreqscs) { |
||||
if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && |
||||
(core_if->core_params->i2c_enable)) { |
||||
core_if->srp_success = 1; |
||||
} |
||||
else { |
||||
pcd_resume(core_if); |
||||
/* Clear Session Request */ |
||||
gotgctl.d32 = 0; |
||||
gotgctl.b.sesreq = 1; |
||||
dwc_modify_reg32(&global_regs->gotgctl, |
||||
gotgctl.d32, 0); |
||||
} |
||||
} |
||||
} |
||||
if (gotgint.b.hstnegsucstschng) { |
||||
/* Print statements during the HNP interrupt handling
|
||||
* can cause it to fail.*/ |
||||
gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); |
||||
if (gotgctl.b.hstnegscs) { |
||||
if (dwc_otg_is_host_mode(core_if)) { |
||||
core_if->op_state = B_HOST; |
||||
/*
|
||||
* Need to disable SOF interrupt immediately. |
||||
* When switching from device to host, the PCD |
||||
* interrupt handler won't handle the |
||||
* interrupt if host mode is already set. The |
||||
* HCD interrupt handler won't get called if |
||||
* the HCD state is HALT. This means that the |
||||
* interrupt does not get handled and Linux |
||||
* complains loudly. |
||||
*/ |
||||
gintmsk.d32 = 0; |
||||
gintmsk.b.sofintr = 1; |
||||
dwc_modify_reg32(&global_regs->gintmsk, |
||||
gintmsk.d32, 0); |
||||
pcd_stop(core_if); |
||||
/*
|
||||
* Initialize the Core for Host mode. |
||||
*/ |
||||
hcd_start(core_if); |
||||
core_if->op_state = B_HOST; |
||||
} |
||||
} else { |
||||
gotgctl.d32 = 0; |
||||
gotgctl.b.hnpreq = 1; |
||||
gotgctl.b.devhnpen = 1; |
||||
dwc_modify_reg32(&global_regs->gotgctl, |
||||
gotgctl.d32, 0); |
||||
DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); |
||||
DWC_ERROR("Device Not Connected/Responding\n"); |
||||
} |
||||
} |
||||
if (gotgint.b.hstnegdet) { |
||||
/* The disconnect interrupt is set at the same time as
|
||||
* Host Negotiation Detected. During the mode |
||||
* switch all interrupts are cleared so the disconnect |
||||
* interrupt handler will not get executed. |
||||
*/ |
||||
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " |
||||
"Host Negotiation Detected++ (%s)\n", |
||||
(dwc_otg_is_host_mode(core_if)?"Host":"Device")); |
||||
if (dwc_otg_is_device_mode(core_if)){ |
||||
DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", core_if->op_state); |
||||
hcd_disconnect(core_if); |
||||
pcd_start(core_if); |
||||
core_if->op_state = A_PERIPHERAL; |
||||
} else { |
||||
/*
|
||||
* Need to disable SOF interrupt immediately. When |
||||
* switching from device to host, the PCD interrupt |
||||
* handler won't handle the interrupt if host mode is |
||||
* already set. The HCD interrupt handler won't get |
||||
* called if the HCD state is HALT. This means that |
||||
* the interrupt does not get handled and Linux |
||||
* complains loudly. |
||||
*/ |
||||
gintmsk.d32 = 0; |
||||
gintmsk.b.sofintr = 1; |
||||
dwc_modify_reg32(&global_regs->gintmsk, |
||||
gintmsk.d32, 0); |
||||
pcd_stop(core_if); |
||||
hcd_start(core_if); |
||||
core_if->op_state = A_HOST; |
||||
} |
||||
} |
||||
if (gotgint.b.adevtoutchng) { |
||||
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " |
||||
"A-Device Timeout Change++\n"); |
||||
} |
||||
if (gotgint.b.debdone) { |
||||
DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " |
||||
"Debounce Done++\n"); |
||||
} |
||||
|
||||
/* Clear GOTGINT */ |
||||
dwc_write_reg32 (&core_if->core_global_regs->gotgint, gotgint.d32); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) |
||||
|
||||
void w_conn_id_status_change(void *p) |
||||
{ |
||||
dwc_otg_core_if_t *core_if = p; |
||||
|
||||
#else |
||||
|
||||
void w_conn_id_status_change(struct work_struct *p) |
||||
{ |
||||
dwc_otg_core_if_t *core_if = container_of(p, dwc_otg_core_if_t, w_conn_id); |
||||
|
||||
#endif |
||||
|
||||
|
||||
uint32_t count = 0; |
||||
gotgctl_data_t gotgctl = { .d32 = 0 }; |
||||
|
||||
gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); |
||||
DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); |
||||
DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); |
||||
|
||||
/* B-Device connector (Device Mode) */ |
||||
if (gotgctl.b.conidsts) { |
||||
/* Wait for switch to device mode. */ |
||||
while (!dwc_otg_is_device_mode(core_if)){ |
||||
DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n", |
||||
(dwc_otg_is_host_mode(core_if)?"Host":"Peripheral")); |
||||
MDELAY(100); |
||||
if (++count > 10000) *(uint32_t*)NULL=0; |
||||
} |
||||
core_if->op_state = B_PERIPHERAL; |
||||
dwc_otg_core_init(core_if); |
||||
dwc_otg_enable_global_interrupts(core_if); |
||||
pcd_start(core_if); |
||||
} else { |
||||
/* A-Device connector (Host Mode) */ |
||||
while (!dwc_otg_is_host_mode(core_if)) { |
||||
DWC_PRINT("Waiting for Host Mode, Mode=%s\n", |
||||
(dwc_otg_is_host_mode(core_if)?"Host":"Peripheral")); |
||||
MDELAY(100); |
||||
if (++count > 10000) *(uint32_t*)NULL=0; |
||||
} |
||||
core_if->op_state = A_HOST; |
||||
/*
|
||||
* Initialize the Core for Host mode. |
||||
*/ |
||||
dwc_otg_core_init(core_if); |
||||
dwc_otg_enable_global_interrupts(core_if); |
||||
hcd_start(core_if); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* This function handles the Connector ID Status Change Interrupt. It |
||||
* reads the OTG Interrupt Register (GOTCTL) to determine whether this |
||||
* is a Device to Host Mode transition or a Host Mode to Device |
||||
* Transition. |
||||
* |
||||
* This only occurs when the cable is connected/removed from the PHY |
||||
* connector. |
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
|
||||
/*
|
||||
* Need to disable SOF interrupt immediately. If switching from device |
||||
* to host, the PCD interrupt handler won't handle the interrupt if |
||||
* host mode is already set. The HCD interrupt handler won't get |
||||
* called if the HCD state is HALT. This means that the interrupt does |
||||
* not get handled and Linux complains loudly. |
||||
*/ |
||||
gintmsk_data_t gintmsk = { .d32 = 0 }; |
||||
gintsts_data_t gintsts = { .d32 = 0 }; |
||||
|
||||
gintmsk.b.sofintr = 1; |
||||
dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); |
||||
|
||||
DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n", |
||||
(dwc_otg_is_host_mode(core_if)?"Host":"Device")); |
||||
|
||||
/*
|
||||
* Need to schedule a work, as there are possible DELAY function calls |
||||
*/ |
||||
queue_work(core_if->wq_otg, &core_if->w_conn_id); |
||||
|
||||
/* Set flag and clear interrupt */ |
||||
gintsts.b.conidstschng = 1; |
||||
dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
/**
|
||||
* This interrupt indicates that a device is initiating the Session |
||||
* Request Protocol to request the host to turn on bus power so a new |
||||
* session can begin. The handler responds by turning on bus power. If |
||||
* the DWC_otg controller is in low power mode, the handler brings the |
||||
* controller out of low power mode before turning on bus power. |
||||
* |
||||
* @param core_if Programming view of DWC_otg controller. |
||||
*/ |
||||
int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
gintsts_data_t gintsts; |
||||
|
||||
#ifndef DWC_HOST_ONLY |
||||
hprt0_data_t hprt0; |
||||
DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); |
||||
|
||||
if (dwc_otg_is_device_mode(core_if)) { |
||||
DWC_PRINT("SRP: Device mode\n"); |
||||
} else { |
||||
DWC_PRINT("SRP: Host mode\n"); |
||||
|
||||
/* Turn on the port power bit. */ |
||||
hprt0.d32 = dwc_otg_read_hprt0(core_if); |
||||
hprt0.b.prtpwr = 1; |
||||
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); |
||||
|
||||
/* Start the Connection timer. So a message can be displayed
|
||||
* if connect does not occur within 10 seconds. */ |
||||
hcd_session_start(core_if); |
||||
} |
||||
#endif |
||||
|
||||
/* Clear interrupt */ |
||||
gintsts.d32 = 0; |
||||
gintsts.b.sessreqintr = 1; |
||||
dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) |
||||
void w_wakeup_detected(void *p) |
||||
{ |
||||
dwc_otg_core_if_t* core_if = p; |
||||
|
||||
#else |
||||
|
||||
void w_wakeup_detected(struct work_struct *p) |
||||
{ |
||||
struct delayed_work *dw = container_of(p, struct delayed_work, work); |
||||
dwc_otg_core_if_t *core_if = container_of(dw, dwc_otg_core_if_t, w_wkp); |
||||
|
||||
#endif |
||||
/*
|
||||
* Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms |
||||
* so that OPT tests pass with all PHYs). |
||||
*/ |
||||
hprt0_data_t hprt0 = {.d32=0}; |
||||
#if 0 |
||||
pcgcctl_data_t pcgcctl = {.d32=0}; |
||||
/* Restart the Phy Clock */ |
||||
pcgcctl.b.stoppclk = 1; |
||||
dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); |
||||
UDELAY(10); |
||||
#endif //0
|
||||
hprt0.d32 = dwc_otg_read_hprt0(core_if); |
||||
DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); |
||||
// MDELAY(70);
|
||||
hprt0.b.prtres = 0; /* Resume */ |
||||
dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); |
||||
DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(core_if->host_if->hprt0)); |
||||
} |
||||
/**
|
||||
* This interrupt indicates that the DWC_otg controller has detected a |
||||
* resume or remote wakeup sequence. If the DWC_otg controller is in |
||||
* low power mode, the handler must brings the controller out of low |
||||
* power mode. The controller automatically begins resume |
||||
* signaling. The handler schedules a time to stop resume signaling. |
||||
*/ |
||||
int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
gintsts_data_t gintsts; |
||||
|
||||
DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); |
||||
|
||||
if (dwc_otg_is_device_mode(core_if)) { |
||||
dctl_data_t dctl = {.d32=0}; |
||||
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", |
||||
dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts)); |
||||
#ifdef PARTIAL_POWER_DOWN |
||||
if (core_if->hwcfg4.b.power_optimiz) { |
||||
pcgcctl_data_t power = {.d32=0}; |
||||
|
||||
power.d32 = dwc_read_reg32(core_if->pcgcctl); |
||||
DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32); |
||||
|
||||
power.b.stoppclk = 0; |
||||
dwc_write_reg32(core_if->pcgcctl, power.d32); |
||||
|
||||
power.b.pwrclmp = 0; |
||||
dwc_write_reg32(core_if->pcgcctl, power.d32); |
||||
|
||||
power.b.rstpdwnmodule = 0; |
||||
dwc_write_reg32(core_if->pcgcctl, power.d32); |
||||
} |
||||
#endif |
||||
/* Clear the Remote Wakeup Signalling */ |
||||
dctl.b.rmtwkupsig = 1; |
||||
dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, |
||||
dctl.d32, 0); |
||||
|
||||
if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { |
||||
core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); |
||||
} |
||||
|
||||
} else { |
||||
pcgcctl_data_t pcgcctl = {.d32=0}; |
||||
|
||||
/* Restart the Phy Clock */ |
||||
pcgcctl.b.stoppclk = 1; |
||||
dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); |
||||
|
||||
queue_delayed_work(core_if->wq_otg, &core_if->w_wkp, ((70 * HZ / 1000) + 1)); |
||||
} |
||||
|
||||
/* Clear interrupt */ |
||||
gintsts.d32 = 0; |
||||
gintsts.b.wkupintr = 1; |
||||
dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
/**
|
||||
* This interrupt indicates that a device has been disconnected from |
||||
* the root port. |
||||
*/ |
||||
int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
gintsts_data_t gintsts; |
||||
|
||||
DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", |
||||
(dwc_otg_is_host_mode(core_if)?"Host":"Device"), |
||||
op_state_str(core_if)); |
||||
|
||||
/** @todo Consolidate this if statement. */ |
||||
#ifndef DWC_HOST_ONLY |
||||
if (core_if->op_state == B_HOST) { |
||||
/* If in device mode Disconnect and stop the HCD, then
|
||||
* start the PCD. */ |
||||
hcd_disconnect(core_if); |
||||
pcd_start(core_if); |
||||
core_if->op_state = B_PERIPHERAL; |
||||
} else if (dwc_otg_is_device_mode(core_if)) { |
||||
gotgctl_data_t gotgctl = { .d32 = 0 }; |
||||
gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); |
||||
if (gotgctl.b.hstsethnpen==1) { |
||||
/* Do nothing, if HNP in process the OTG
|
||||
* interrupt "Host Negotiation Detected" |
||||
* interrupt will do the mode switch. |
||||
*/ |
||||
} else if (gotgctl.b.devhnpen == 0) { |
||||
/* If in device mode Disconnect and stop the HCD, then
|
||||
* start the PCD. */ |
||||
hcd_disconnect(core_if); |
||||
pcd_start(core_if); |
||||
core_if->op_state = B_PERIPHERAL; |
||||
} else { |
||||
DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n"); |
||||
} |
||||
} else { |
||||
if (core_if->op_state == A_HOST) { |
||||
/* A-Cable still connected but device disconnected. */ |
||||
hcd_disconnect(core_if); |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
gintsts.d32 = 0; |
||||
gintsts.b.disconnect = 1; |
||||
dwc_write_reg32 (&core_if->core_global_regs->gintsts, gintsts.d32); |
||||
return 1; |
||||
} |
||||
/**
|
||||
* This interrupt indicates that SUSPEND state has been detected on |
||||
* the USB. |
||||
* |
||||
* For HNP the USB Suspend interrupt signals the change from |
||||
* "a_peripheral" to "a_host". |
||||
* |
||||
* When power management is enabled the core will be put in low power |
||||
* mode. |
||||
*/ |
||||
int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
dsts_data_t dsts; |
||||
gintsts_data_t gintsts; |
||||
|
||||
DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n"); |
||||
|
||||
if (dwc_otg_is_device_mode(core_if)) { |
||||
/* Check the Device status register to determine if the Suspend
|
||||
* state is active. */ |
||||
dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); |
||||
DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); |
||||
DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " |
||||
"HWCFG4.power Optimize=%d\n", |
||||
dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz); |
||||
|
||||
|
||||
#ifdef PARTIAL_POWER_DOWN |
||||
/** @todo Add a module parameter for power management. */ |
||||
|
||||
if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) { |
||||
pcgcctl_data_t power = {.d32=0}; |
||||
DWC_DEBUGPL(DBG_CIL, "suspend\n"); |
||||
|
||||
power.b.pwrclmp = 1; |
||||
dwc_write_reg32(core_if->pcgcctl, power.d32); |
||||
|
||||
power.b.rstpdwnmodule = 1; |
||||
dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); |
||||
|
||||
power.b.stoppclk = 1; |
||||
dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); |
||||
|
||||
} else { |
||||
DWC_DEBUGPL(DBG_ANY,"disconnect?\n"); |
||||
} |
||||
#endif |
||||
/* PCD callback for suspend. */ |
||||
pcd_suspend(core_if); |
||||
} else { |
||||
if (core_if->op_state == A_PERIPHERAL) { |
||||
DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n"); |
||||
/* Clear the a_peripheral flag, back to a_host. */ |
||||
pcd_stop(core_if); |
||||
hcd_start(core_if); |
||||
core_if->op_state = A_HOST; |
||||
} |
||||
} |
||||
|
||||
/* Clear interrupt */ |
||||
gintsts.d32 = 0; |
||||
gintsts.b.usbsuspend = 1; |
||||
dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* This function returns the Core Interrupt register. |
||||
*/ |
||||
static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
gintsts_data_t gintsts; |
||||
gintmsk_data_t gintmsk; |
||||
gintmsk_data_t gintmsk_common = {.d32=0}; |
||||
gintmsk_common.b.wkupintr = 1; |
||||
gintmsk_common.b.sessreqintr = 1; |
||||
gintmsk_common.b.conidstschng = 1; |
||||
gintmsk_common.b.otgintr = 1; |
||||
gintmsk_common.b.modemismatch = 1; |
||||
gintmsk_common.b.disconnect = 1; |
||||
gintmsk_common.b.usbsuspend = 1; |
||||
/** @todo: The port interrupt occurs while in device
|
||||
* mode. Added code to CIL to clear the interrupt for now! |
||||
*/ |
||||
gintmsk_common.b.portintr = 1; |
||||
|
||||
gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts); |
||||
gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk); |
||||
#ifdef DEBUG |
||||
/* if any common interrupts set */ |
||||
if (gintsts.d32 & gintmsk_common.d32) { |
||||
DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n", |
||||
gintsts.d32, gintmsk.d32); |
||||
} |
||||
#endif |
||||
|
||||
return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); |
||||
|
||||
} |
||||
|
||||
/**
|
||||
* Common interrupt handler. |
||||
* |
||||
* The common interrupts are those that occur in both Host and Device mode. |
||||
* This handler handles the following interrupts: |
||||
* - Mode Mismatch Interrupt |
||||
* - Disconnect Interrupt |
||||
* - OTG Interrupt |
||||
* - Connector ID Status Change Interrupt |
||||
* - Session Request Interrupt. |
||||
* - Resume / Remote Wakeup Detected Interrupt. |
||||
* |
||||
*/ |
||||
int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t *core_if) |
||||
{ |
||||
int retval = 0; |
||||
gintsts_data_t gintsts; |
||||
|
||||
gintsts.d32 = dwc_otg_read_common_intr(core_if); |
||||
|
||||
if (gintsts.b.modemismatch) { |
||||
retval |= dwc_otg_handle_mode_mismatch_intr(core_if); |
||||
} |
||||
if (gintsts.b.otgintr) { |
||||
retval |= dwc_otg_handle_otg_intr(core_if); |
||||
} |
||||
if (gintsts.b.conidstschng) { |
||||
retval |= dwc_otg_handle_conn_id_status_change_intr(core_if); |
||||
} |
||||
if (gintsts.b.disconnect) { |
||||
retval |= dwc_otg_handle_disconnect_intr(core_if); |
||||
} |
||||
if (gintsts.b.sessreqintr) { |
||||
retval |= dwc_otg_handle_session_req_intr(core_if); |
||||
} |
||||
if (gintsts.b.wkupintr) { |
||||
retval |= dwc_otg_handle_wakeup_detected_intr(core_if); |
||||
} |
||||
if (gintsts.b.usbsuspend) { |
||||
retval |= dwc_otg_handle_usb_suspend_intr(core_if); |
||||
} |
||||
if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { |
||||
/* The port interrupt occurs while in device mode with HPRT0
|
||||
* Port Enable/Disable. |
||||
*/ |
||||
gintsts.d32 = 0; |
||||
gintsts.b.portintr = 1; |
||||
dwc_write_reg32(&core_if->core_global_regs->gintsts, |
||||
gintsts.d32); |
||||
retval |= 1; |
||||
|
||||
} |
||||
|
||||
S3C2410X_CLEAR_EINTPEND(); |
||||
|
||||
return retval; |
||||
} |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,83 @@ |
||||
/* ==========================================================================
|
||||
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
|
||||
* $Revision: 1.2 $ |
||||
* $Date: 2008-11-21 05:39:15 $ |
||||
* $Change: 1064918 $ |
||||
* |
||||
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
||||
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
||||
* otherwise expressly agreed to in writing between Synopsys and you. |
||||
* |
||||
* The Software IS NOT an item of Licensed Software or Licensed Product under |
||||
* any End User Software License Agreement or Agreement for Licensed Product |
||||
* with Synopsys or any supplement thereto. You are permitted to use and |
||||
* redistribute this Software in source and binary forms, with or without |
||||
* modification, provided that redistributions of source code must retain this |
||||
* notice. You may not view, use, disclose, copy or distribute this file or |
||||
* any information contained herein except pursuant to this license grant from |
||||
* Synopsys. If you do not agree with this notice, including the disclaimer |
||||
* below, then you are not authorized to use the Software. |
||||
* |
||||
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
||||
* DAMAGE. |
||||
* ========================================================================== */ |
||||
|
||||
#ifndef __DWC_OTG_DRIVER_H__ |
||||
#define __DWC_OTG_DRIVER_H__ |
||||
|
||||
/** @file
|
||||
* This file contains the interface to the Linux driver. |
||||
*/ |
||||
#include "dwc_otg_cil.h" |
||||
|
||||
/* Type declarations */ |
||||
struct dwc_otg_pcd; |
||||
struct dwc_otg_hcd; |
||||
|
||||
/**
|
||||
* This structure is a wrapper that encapsulates the driver components used to |
||||
* manage a single DWC_otg controller. |
||||
*/ |
||||
typedef struct dwc_otg_device { |
||||
/** Base address returned from ioremap() */ |
||||
void *base; |
||||
|
||||
struct device *parent; |
||||
|
||||
/** Pointer to the core interface structure. */ |
||||
dwc_otg_core_if_t *core_if; |
||||
|
||||
/** Register offset for Diagnostic API. */ |
||||
uint32_t reg_offset; |
||||
|
||||
/** Pointer to the PCD structure. */ |
||||
struct dwc_otg_pcd *pcd; |
||||
|
||||
/** Pointer to the HCD structure. */ |
||||
struct dwc_otg_hcd *hcd; |
||||
|
||||
/** Flag to indicate whether the common IRQ handler is installed. */ |
||||
uint8_t common_irq_installed; |
||||
|
||||
/* Interrupt request number. */ |
||||
unsigned int irq; |
||||
|
||||
/* Physical address of Control and Status registers, used by
|
||||
* release_mem_region(). |
||||
*/ |
||||
resource_size_t phys_addr; |
||||
|
||||
/* Length of memory region, used by release_mem_region(). */ |
||||
unsigned long base_len; |
||||
} dwc_otg_device_t; |
||||
|
||||
#endif |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,664 @@ |
||||
/* ==========================================================================
|
||||
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
|
||||
* $Revision: 1.3 $ |
||||
* $Date: 2008-12-15 06:51:32 $ |
||||
* $Change: 1064918 $ |
||||
* |
||||
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
||||
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
||||
* otherwise expressly agreed to in writing between Synopsys and you. |
||||
* |
||||
* The Software IS NOT an item of Licensed Software or Licensed Product under |
||||
* any End User Software License Agreement or Agreement for Licensed Product |
||||
* with Synopsys or any supplement thereto. You are permitted to use and |
||||
* redistribute this Software in source and binary forms, with or without |
||||
* modification, provided that redistributions of source code must retain this |
||||
* notice. You may not view, use, disclose, copy or distribute this file or |
||||
* any information contained herein except pursuant to this license grant from |
||||
* Synopsys. If you do not agree with this notice, including the disclaimer |
||||
* below, then you are not authorized to use the Software. |
||||
* |
||||
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
||||
* DAMAGE. |
||||
* ========================================================================== */ |
||||
#ifndef DWC_DEVICE_ONLY |
||||
#ifndef __DWC_HCD_H__ |
||||
#define __DWC_HCD_H__ |
||||
|
||||
#include <linux/list.h> |
||||
#include <linux/usb.h> |
||||
#include <linux/usb/hcd.h> |
||||
|
||||
struct dwc_otg_device; |
||||
|
||||
#include "dwc_otg_cil.h" |
||||
|
||||
/**
|
||||
* @file |
||||
* |
||||
* This file contains the structures, constants, and interfaces for |
||||
* the Host Contoller Driver (HCD). |
||||
* |
||||
* The Host Controller Driver (HCD) is responsible for translating requests |
||||
* from the USB Driver into the appropriate actions on the DWC_otg controller. |
||||
* It isolates the USBD from the specifics of the controller by providing an |
||||
* API to the USBD. |
||||
*/ |
||||
|
||||
/**
|
||||
* Phases for control transfers. |
||||
*/ |
||||
typedef enum dwc_otg_control_phase { |
||||
DWC_OTG_CONTROL_SETUP, |
||||
DWC_OTG_CONTROL_DATA, |
||||
DWC_OTG_CONTROL_STATUS |
||||
} dwc_otg_control_phase_e; |
||||
|
||||
/** Transaction types. */ |
||||
typedef enum dwc_otg_transaction_type { |
||||
DWC_OTG_TRANSACTION_NONE, |
||||
DWC_OTG_TRANSACTION_PERIODIC, |
||||
DWC_OTG_TRANSACTION_NON_PERIODIC, |
||||
DWC_OTG_TRANSACTION_ALL |
||||
} dwc_otg_transaction_type_e; |
||||
|
||||
/**
|
||||
* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, |
||||
* interrupt, or isochronous transfer. A single QTD is created for each URB |
||||
* (of one of these types) submitted to the HCD. The transfer associated with |
||||
* a QTD may require one or multiple transactions. |
||||
* |
||||
* A QTD is linked to a Queue Head, which is entered in either the |
||||
* non-periodic or periodic schedule for execution. When a QTD is chosen for |
||||
* execution, some or all of its transactions may be executed. After |
||||
* execution, the state of the QTD is updated. The QTD may be retired if all |
||||
* its transactions are complete or if an error occurred. Otherwise, it |
||||
* remains in the schedule so more transactions can be executed later. |
||||
*/ |
||||
typedef struct dwc_otg_qtd { |
||||
/**
|
||||
* Determines the PID of the next data packet for the data phase of |
||||
* control transfers. Ignored for other transfer types.<br> |
||||
* One of the following values: |
||||
* - DWC_OTG_HC_PID_DATA0 |
||||
* - DWC_OTG_HC_PID_DATA1 |
||||
*/ |
||||
uint8_t data_toggle; |
||||
|
||||
/** Current phase for control transfers (Setup, Data, or Status). */ |
||||
dwc_otg_control_phase_e control_phase; |
||||
|
||||
/** Keep track of the current split type
|
||||
* for FS/LS endpoints on a HS Hub */ |
||||
uint8_t complete_split; |
||||
|
||||
/** How many bytes transferred during SSPLIT OUT */ |
||||
uint32_t ssplit_out_xfer_count; |
||||
|
||||
/**
|
||||
* Holds the number of bus errors that have occurred for a transaction |
||||
* within this transfer. |
||||
*/ |
||||
uint8_t error_count; |
||||
|
||||
/**
|
||||
* Index of the next frame descriptor for an isochronous transfer. A |
||||
* frame descriptor describes the buffer position and length of the |
||||
* data to be transferred in the next scheduled (micro)frame of an |
||||
* isochronous transfer. It also holds status for that transaction. |
||||
* The frame index starts at 0. |
||||
*/ |
||||
int isoc_frame_index; |
||||
|
||||
/** Position of the ISOC split on full/low speed */ |
||||
uint8_t isoc_split_pos; |
||||
|
||||
/** Position of the ISOC split in the buffer for the current frame */ |
||||
uint16_t isoc_split_offset; |
||||
|
||||
/** URB for this transfer */ |
||||
struct urb *urb; |
||||
|
||||
/** This list of QTDs */ |
||||
struct list_head qtd_list_entry; |
||||
|
||||
} dwc_otg_qtd_t; |
||||
|
||||
/**
|
||||
* A Queue Head (QH) holds the static characteristics of an endpoint and |
||||
* maintains a list of transfers (QTDs) for that endpoint. A QH structure may |
||||
* be entered in either the non-periodic or periodic schedule. |
||||
*/ |
||||
typedef struct dwc_otg_qh { |
||||
/**
|
||||
* Endpoint type. |
||||
* One of the following values: |
||||
* - USB_ENDPOINT_XFER_CONTROL |
||||
* - USB_ENDPOINT_XFER_ISOC |
||||
* - USB_ENDPOINT_XFER_BULK |
||||
* - USB_ENDPOINT_XFER_INT |
||||
*/ |
||||
uint8_t ep_type; |
||||
uint8_t ep_is_in; |
||||
|
||||
/** wMaxPacketSize Field of Endpoint Descriptor. */ |
||||
uint16_t maxp; |
||||
|
||||
/**
|
||||
* Determines the PID of the next data packet for non-control |
||||
* transfers. Ignored for control transfers.<br> |
||||
* One of the following values: |
||||
* - DWC_OTG_HC_PID_DATA0 |
||||
* - DWC_OTG_HC_PID_DATA1 |
||||
*/ |
||||
uint8_t data_toggle; |
||||
|
||||
/** Ping state if 1. */ |
||||
uint8_t ping_state; |
||||
|
||||
/**
|
||||
* List of QTDs for this QH. |
||||
*/ |
||||
struct list_head qtd_list; |
||||
|
||||
/** Host channel currently processing transfers for this QH. */ |
||||
dwc_hc_t *channel; |
||||
|
||||
/** QTD currently assigned to a host channel for this QH. */ |
||||
dwc_otg_qtd_t *qtd_in_process; |
||||
|
||||
/** Full/low speed endpoint on high-speed hub requires split. */ |
||||
uint8_t do_split; |
||||
|
||||
/** @name Periodic schedule information */ |
||||
/** @{ */ |
||||
|
||||
/** Bandwidth in microseconds per (micro)frame. */ |
||||
uint8_t usecs; |
||||
|
||||
/** Interval between transfers in (micro)frames. */ |
||||
uint16_t interval; |
||||
|
||||
/**
|
||||
* (micro)frame to initialize a periodic transfer. The transfer |
||||
* executes in the following (micro)frame. |
||||
*/ |
||||
uint16_t sched_frame; |
||||
|
||||
/** (micro)frame at which last start split was initialized. */ |
||||
uint16_t start_split_frame; |
||||
|
||||
/** @} */ |
||||
|
||||
/** Entry for QH in either the periodic or non-periodic schedule. */ |
||||
struct list_head qh_list_entry; |
||||
|
||||
/* For non-dword aligned buffer support */ |
||||
uint8_t *dw_align_buf; |
||||
dma_addr_t dw_align_buf_dma; |
||||
} dwc_otg_qh_t; |
||||
|
||||
/**
|
||||
* This structure holds the state of the HCD, including the non-periodic and |
||||
* periodic schedules. |
||||
*/ |
||||
typedef struct dwc_otg_hcd { |
||||
/** The DWC otg device pointer */ |
||||
struct dwc_otg_device *otg_dev; |
||||
|
||||
/** DWC OTG Core Interface Layer */ |
||||
dwc_otg_core_if_t *core_if; |
||||
|
||||
/** Internal DWC HCD Flags */ |
||||
volatile union dwc_otg_hcd_internal_flags { |
||||
uint32_t d32; |
||||
struct { |
||||
unsigned port_connect_status_change : 1; |
||||
unsigned port_connect_status : 1; |
||||
unsigned port_reset_change : 1; |
||||
unsigned port_enable_change : 1; |
||||
unsigned port_suspend_change : 1; |
||||
unsigned port_over_current_change : 1; |
||||
unsigned reserved : 27; |
||||
} b; |
||||
} flags; |
||||
|
||||
/**
|
||||
* Inactive items in the non-periodic schedule. This is a list of |
||||
* Queue Heads. Transfers associated with these Queue Heads are not |
||||
* currently assigned to a host channel. |
||||
*/ |
||||
struct list_head non_periodic_sched_inactive; |
||||
|
||||
/**
|
||||
* Active items in the non-periodic schedule. This is a list of |
||||
* Queue Heads. Transfers associated with these Queue Heads are |
||||
* currently assigned to a host channel. |
||||
*/ |
||||
struct list_head non_periodic_sched_active; |
||||
|
||||
/**
|
||||
* Pointer to the next Queue Head to process in the active |
||||
* non-periodic schedule. |
||||
*/ |
||||
struct list_head *non_periodic_qh_ptr; |
||||
|
||||
/**
|
||||
* Inactive items in the periodic schedule. This is a list of QHs for |
||||
* periodic transfers that are _not_ scheduled for the next frame. |
||||
* Each QH in the list has an interval counter that determines when it |
||||
* needs to be scheduled for execution. This scheduling mechanism |
||||
* allows only a simple calculation for periodic bandwidth used (i.e. |
||||
* must assume that all periodic transfers may need to execute in the |
||||
* same frame). However, it greatly simplifies scheduling and should |
||||
* be sufficient for the vast majority of OTG hosts, which need to |
||||
* connect to a small number of peripherals at one time. |
||||
* |
||||
* Items move from this list to periodic_sched_ready when the QH |
||||
* interval counter is 0 at SOF. |
||||
*/ |
||||
struct list_head periodic_sched_inactive; |
||||
|
||||
/**
|
||||
* List of periodic QHs that are ready for execution in the next |
||||
* frame, but have not yet been assigned to host channels. |
||||
* |
||||
* Items move from this list to periodic_sched_assigned as host |
||||
* channels become available during the current frame. |
||||
*/ |
||||
struct list_head periodic_sched_ready; |
||||
|
||||
/**
|
||||
* List of periodic QHs to be executed in the next frame that are |
||||
* assigned to host channels. |
||||
* |
||||
* Items move from this list to periodic_sched_queued as the |
||||
* transactions for the QH are queued to the DWC_otg controller. |
||||
*/ |
||||
struct list_head periodic_sched_assigned; |
||||
|
||||
/**
|
||||
* List of periodic QHs that have been queued for execution. |
||||
* |
||||
* Items move from this list to either periodic_sched_inactive or |
||||
* periodic_sched_ready when the channel associated with the transfer |
||||
* is released. If the interval for the QH is 1, the item moves to |
||||
* periodic_sched_ready because it must be rescheduled for the next |
||||
* frame. Otherwise, the item moves to periodic_sched_inactive. |
||||
*/ |
||||
struct list_head periodic_sched_queued; |
||||
|
||||
/**
|
||||
* Total bandwidth claimed so far for periodic transfers. This value |
||||
* is in microseconds per (micro)frame. The assumption is that all |
||||
* periodic transfers may occur in the same (micro)frame. |
||||
*/ |
||||
uint16_t periodic_usecs; |
||||
|
||||
/**
|
||||
* Frame number read from the core at SOF. The value ranges from 0 to |
||||
* DWC_HFNUM_MAX_FRNUM. |
||||
*/ |
||||
uint16_t frame_number; |
||||
|
||||
/**
|
||||
* Free host channels in the controller. This is a list of |
||||
* dwc_hc_t items. |
||||
*/ |
||||
struct list_head free_hc_list; |
||||
|
||||
/**
|
||||
* Number of host channels assigned to periodic transfers. Currently |
||||
* assuming that there is a dedicated host channel for each periodic |
||||
* transaction and at least one host channel available for |
||||
* non-periodic transactions. |
||||
*/ |
||||
int periodic_channels; |
||||
|
||||
/**
|
||||
* Number of host channels assigned to non-periodic transfers. |
||||
*/ |
||||
int non_periodic_channels; |
||||
|
||||
/**
|
||||
* Array of pointers to the host channel descriptors. Allows accessing |
||||
* a host channel descriptor given the host channel number. This is |
||||
* useful in interrupt handlers. |
||||
*/ |
||||
dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS]; |
||||
|
||||
/**
|
||||
* Buffer to use for any data received during the status phase of a |
||||
* control transfer. Normally no data is transferred during the status |
||||
* phase. This buffer is used as a bit bucket. |
||||
*/ |
||||
uint8_t *status_buf; |
||||
|
||||
/**
|
||||
* DMA address for status_buf. |
||||
*/ |
||||
dma_addr_t status_buf_dma; |
||||
#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 |
||||
|
||||
/**
|
||||
* Structure to allow starting the HCD in a non-interrupt context |
||||
* during an OTG role change. |
||||
*/ |
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) |
||||
struct work_struct start_work; |
||||
#else |
||||
struct delayed_work start_work; |
||||
#endif |
||||
|
||||
/**
|
||||
* Connection timer. An OTG host must display a message if the device |
||||
* does not connect. Started when the VBus power is turned on via |
||||
* sysfs attribute "buspower". |
||||
*/ |
||||
struct timer_list conn_timer; |
||||
|
||||
/* Tasket to do a reset */ |
||||
struct tasklet_struct *reset_tasklet; |
||||
|
||||
/* */ |
||||
spinlock_t lock; |
||||
|
||||
#ifdef DEBUG |
||||
uint32_t frrem_samples; |
||||
uint64_t frrem_accum; |
||||
|
||||
uint32_t hfnum_7_samples_a; |
||||
uint64_t hfnum_7_frrem_accum_a; |
||||
uint32_t hfnum_0_samples_a; |
||||
uint64_t hfnum_0_frrem_accum_a; |
||||
uint32_t hfnum_other_samples_a; |
||||
uint64_t hfnum_other_frrem_accum_a; |
||||
|
||||
uint32_t hfnum_7_samples_b; |
||||
uint64_t hfnum_7_frrem_accum_b; |
||||
uint32_t hfnum_0_samples_b; |
||||
uint64_t hfnum_0_frrem_accum_b; |
||||
uint32_t hfnum_other_samples_b; |
||||
uint64_t hfnum_other_frrem_accum_b; |
||||
#endif |
||||
} dwc_otg_hcd_t; |
||||
|
||||
/** Gets the dwc_otg_hcd from a struct usb_hcd */ |
||||
static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) |
||||
{ |
||||
return (dwc_otg_hcd_t *)(hcd->hcd_priv); |
||||
} |
||||
|
||||
/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ |
||||
static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd) |
||||
{ |
||||
return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv); |
||||
} |
||||
|
||||
/** @name HCD Create/Destroy Functions */ |
||||
/** @{ */ |
||||
extern int dwc_otg_hcd_init(struct device *dev); |
||||
extern void dwc_otg_hcd_remove(struct device *dev); |
||||
/** @} */ |
||||
|
||||
/** @name Linux HC Driver API Functions */ |
||||
/** @{ */ |
||||
|
||||
extern int dwc_otg_hcd_start(struct usb_hcd *hcd); |
||||
extern void dwc_otg_hcd_stop(struct usb_hcd *hcd); |
||||
extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd); |
||||
extern void dwc_otg_hcd_free(struct usb_hcd *hcd); |
||||
extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, |
||||
struct urb *urb, |
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) |
||||
int mem_flags |
||||
#else |
||||
gfp_t mem_flags |
||||
#endif |
||||
); |
||||
extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, |
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) |
||||
#endif |
||||
struct urb *urb, int status); |
||||
extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, |
||||
struct usb_host_endpoint *ep); |
||||
extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd |
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) |
||||
, struct pt_regs *regs |
||||
#endif |
||||
); |
||||
extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, |
||||
char *buf); |
||||
extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, |
||||
u16 typeReq, |
||||
u16 wValue, |
||||
u16 wIndex, |
||||
char *buf, |
||||
u16 wLength); |
||||
|
||||
/** @} */ |
||||
|
||||
/** @name Transaction Execution Functions */ |
||||
/** @{ */ |
||||
extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd); |
||||
extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd, |
||||
dwc_otg_transaction_type_e tr_type); |
||||
extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb, |
||||
int status); |
||||
/** @} */ |
||||
|
||||
/** @name Interrupt Handler Functions */ |
||||
/** @{ */ |
||||
extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num); |
||||
extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd); |
||||
/** @} */ |
||||
|
||||
|
||||
/** @name Schedule Queue Functions */ |
||||
/** @{ */ |
||||
|
||||
/* Implemented in dwc_otg_hcd_queue.c */ |
||||
extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb); |
||||
extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb); |
||||
extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); |
||||
extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); |
||||
extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); |
||||
extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit); |
||||
|
||||
/** Remove and free a QH */ |
||||
static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd, |
||||
dwc_otg_qh_t *qh) |
||||
{ |
||||
dwc_otg_hcd_qh_remove(hcd, qh); |
||||
dwc_otg_hcd_qh_free(hcd, qh); |
||||
} |
||||
|
||||
/** Allocates memory for a QH structure.
|
||||
* @return Returns the memory allocate or NULL on error. */ |
||||
static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void) |
||||
{ |
||||
return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL); |
||||
} |
||||
|
||||
extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb); |
||||
extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb); |
||||
extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd); |
||||
|
||||
/** Allocates memory for a QTD structure.
|
||||
* @return Returns the memory allocate or NULL on error. */ |
||||
static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void) |
||||
{ |
||||
return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL); |
||||
} |
||||
|
||||
/** Frees the memory for a QTD structure. QTD should already be removed from
|
||||
* list. |
||||
* @param[in] qtd QTD to free.*/ |
||||
static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd) |
||||
{ |
||||
kfree(qtd); |
||||
} |
||||
|
||||
/** Removes a QTD from list.
|
||||
* @param[in] hcd HCD instance. |
||||
* @param[in] qtd QTD to remove from list. */ |
||||
static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd) |
||||
{ |
||||
unsigned long flags; |
||||
SPIN_LOCK_IRQSAVE(&hcd->lock, flags); |
||||
list_del(&qtd->qtd_list_entry); |
||||
SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags); |
||||
} |
||||
|
||||
/** Remove and free a QTD */ |
||||
static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd) |
||||
{ |
||||
dwc_otg_hcd_qtd_remove(hcd, qtd); |
||||
dwc_otg_hcd_qtd_free(qtd); |
||||
} |
||||
|
||||
/** @} */ |
||||
|
||||
|
||||
/** @name Internal Functions */ |
||||
/** @{ */ |
||||
dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb); |
||||
void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd); |
||||
void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd); |
||||
/** @} */ |
||||
|
||||
/** Gets the usb_host_endpoint associated with an URB. */ |
||||
static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb) |
||||
{ |
||||
struct usb_device *dev = urb->dev; |
||||
int ep_num = usb_pipeendpoint(urb->pipe); |
||||
|
||||
if (usb_pipein(urb->pipe)) |
||||
return dev->ep_in[ep_num]; |
||||
else |
||||
return dev->ep_out[ep_num]; |
||||
} |
||||
|
||||
/**
|
||||
* Gets the endpoint number from a _bEndpointAddress argument. The endpoint is |
||||
* qualified with its direction (possible 32 endpoints per device). |
||||
*/ |
||||
#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ |
||||
((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) |
||||
|
||||
/** Gets the QH that contains the list_head */ |
||||
#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) |
||||
|
||||
/** Gets the QTD that contains the list_head */ |
||||
#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) |
||||
|
||||
/** Check if QH is non-periodic */ |
||||
#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \ |
||||
(_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL)) |
||||
|
||||
/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ |
||||
#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) |
||||
|
||||
/** Packet size for any kind of endpoint descriptor */ |
||||
#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
||||
|
||||
/**
|
||||
* Returns true if _frame1 is less than or equal to _frame2. The comparison is |
||||
* done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the |
||||
* frame number when the max frame number is reached. |
||||
*/ |
||||
static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2) |
||||
{ |
||||
return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <= |
||||
(DWC_HFNUM_MAX_FRNUM >> 1); |
||||
} |
||||
|
||||
/**
|
||||
* Returns true if _frame1 is greater than _frame2. The comparison is done |
||||
* modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame |
||||
* number when the max frame number is reached. |
||||
*/ |
||||
static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2) |
||||
{ |
||||
return (frame1 != frame2) && |
||||
(((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) < |
||||
(DWC_HFNUM_MAX_FRNUM >> 1)); |
||||
} |
||||
|
||||
/**
|
||||
* Increments _frame by the amount specified by _inc. The addition is done |
||||
* modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. |
||||
*/ |
||||
static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc) |
||||
{ |
||||
return (frame + inc) & DWC_HFNUM_MAX_FRNUM; |
||||
} |
||||
|
||||
static inline uint16_t dwc_full_frame_num(uint16_t frame) |
||||
{ |
||||
return (frame & DWC_HFNUM_MAX_FRNUM) >> 3; |
||||
} |
||||
|
||||
static inline uint16_t dwc_micro_frame_num(uint16_t frame) |
||||
{ |
||||
return frame & 0x7; |
||||
} |
||||
|
||||
#ifdef DEBUG |
||||
/**
|
||||
* Macro to sample the remaining PHY clocks left in the current frame. This |
||||
* may be used during debugging to determine the average time it takes to |
||||
* execute sections of code. There are two possible sample points, "a" and |
||||
* "b", so the _letter argument must be one of these values. |
||||
* |
||||
* To dump the average sample times, read the "hcd_frrem" sysfs attribute. For |
||||
* example, "cat /sys/devices/lm0/hcd_frrem". |
||||
*/ |
||||
#define dwc_sample_frrem(_hcd, _qh, _letter) \ |
||||
{ \
|
||||
hfnum_data_t hfnum; \
|
||||
dwc_otg_qtd_t *qtd; \
|
||||
qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
|
||||
if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
|
||||
hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
|
||||
switch (hfnum.b.frnum & 0x7) { \
|
||||
case 7: \
|
||||
_hcd->hfnum_7_samples_##_letter++; \
|
||||
_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
|
||||
break; \
|
||||
case 0: \
|
||||
_hcd->hfnum_0_samples_##_letter++; \
|
||||
_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
|
||||
break; \
|
||||
default: \
|
||||
_hcd->hfnum_other_samples_##_letter++; \
|
||||
_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} |
||||
#else |
||||
#define dwc_sample_frrem(_hcd, _qh, _letter) |
||||
#endif |
||||
#endif |
||||
#endif /* DWC_DEVICE_ONLY */ |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,684 @@ |
||||
/* ==========================================================================
|
||||
* $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
|
||||
* $Revision: 1.5 $ |
||||
* $Date: 2008-12-15 06:51:32 $ |
||||
* $Change: 537387 $ |
||||
* |
||||
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
||||
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
||||
* otherwise expressly agreed to in writing between Synopsys and you. |
||||
* |
||||
* The Software IS NOT an item of Licensed Software or Licensed Product under |
||||
* any End User Software License Agreement or Agreement for Licensed Product |
||||
* with Synopsys or any supplement thereto. You are permitted to use and |
||||
* redistribute this Software in source and binary forms, with or without |
||||
* modification, provided that redistributions of source code must retain this |
||||
* notice. You may not view, use, disclose, copy or distribute this file or |
||||
* any information contained herein except pursuant to this license grant from |
||||
* Synopsys. If you do not agree with this notice, including the disclaimer |
||||
* below, then you are not authorized to use the Software. |
||||
* |
||||
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
||||
* DAMAGE. |
||||
* ========================================================================== */ |
||||
#ifndef DWC_DEVICE_ONLY |
||||
|
||||
/**
|
||||
* @file |
||||
* |
||||
* This file contains the functions to manage Queue Heads and Queue |
||||
* Transfer Descriptors. |
||||
*/ |
||||
#include <linux/kernel.h> |
||||
#include <linux/module.h> |
||||
#include <linux/moduleparam.h> |
||||
#include <linux/init.h> |
||||
#include <linux/device.h> |
||||
#include <linux/errno.h> |
||||
#include <linux/list.h> |
||||
#include <linux/interrupt.h> |
||||
#include <linux/string.h> |
||||
#include <linux/dma-mapping.h> |
||||
|
||||
#include "dwc_otg_driver.h" |
||||
#include "dwc_otg_hcd.h" |
||||
#include "dwc_otg_regs.h" |
||||
|
||||
/**
|
||||
* This function allocates and initializes a QH. |
||||
* |
||||
* @param hcd The HCD state structure for the DWC OTG controller. |
||||
* @param[in] urb Holds the information about the device/endpoint that we need |
||||
* to initialize the QH. |
||||
* |
||||
* @return Returns pointer to the newly allocated QH, or NULL on error. */ |
||||
dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, struct urb *urb) |
||||
{ |
||||
dwc_otg_qh_t *qh; |
||||
|
||||
/* Allocate memory */ |
||||
/** @todo add memflags argument */ |
||||
qh = dwc_otg_hcd_qh_alloc (); |
||||
if (qh == NULL) { |
||||
return NULL; |
||||
} |
||||
|
||||
dwc_otg_hcd_qh_init (hcd, qh, urb); |
||||
return qh; |
||||
} |
||||
|
||||
/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
|
||||
* removed from a list. QTD list should already be empty if called from URB |
||||
* Dequeue. |
||||
* |
||||
* @param[in] hcd HCD instance. |
||||
* @param[in] qh The QH to free. |
||||
*/ |
||||
void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) |
||||
{ |
||||
dwc_otg_qtd_t *qtd; |
||||
struct list_head *pos; |
||||
unsigned long flags; |
||||
|
||||
/* Free each QTD in the QTD list */ |
||||
SPIN_LOCK_IRQSAVE(&hcd->lock, flags) |
||||
for (pos = qh->qtd_list.next; |
||||
pos != &qh->qtd_list; |
||||
pos = qh->qtd_list.next) |
||||
{ |
||||
list_del (pos); |
||||
qtd = dwc_list_to_qtd (pos); |
||||
dwc_otg_hcd_qtd_free (qtd); |
||||
} |
||||
SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) |
||||
|
||||
if (qh->dw_align_buf) { |
||||
dma_free_coherent((dwc_otg_hcd_to_hcd(hcd))->self.controller, |
||||
hcd->core_if->core_params->max_transfer_size, |
||||
qh->dw_align_buf, |
||||
qh->dw_align_buf_dma); |
||||
} |
||||
|
||||
kfree (qh); |
||||
return; |
||||
} |
||||
|
||||
/** Initializes a QH structure.
|
||||
* |
||||
* @param[in] hcd The HCD state structure for the DWC OTG controller. |
||||
* @param[in] qh The QH to init. |
||||
* @param[in] urb Holds the information about the device/endpoint that we need |
||||
* to initialize the QH. */ |
||||
#define SCHEDULE_SLOP 10 |
||||
void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb) |
||||
{ |
||||
char *speed, *type; |
||||
memset (qh, 0, sizeof (dwc_otg_qh_t)); |
||||
|
||||
/* Initialize QH */ |
||||
switch (usb_pipetype(urb->pipe)) { |
||||
case PIPE_CONTROL: |
||||
qh->ep_type = USB_ENDPOINT_XFER_CONTROL; |
||||
break; |
||||
case PIPE_BULK: |
||||
qh->ep_type = USB_ENDPOINT_XFER_BULK; |
||||
break; |
||||
case PIPE_ISOCHRONOUS: |
||||
qh->ep_type = USB_ENDPOINT_XFER_ISOC; |
||||
break; |
||||
case PIPE_INTERRUPT: |
||||
qh->ep_type = USB_ENDPOINT_XFER_INT; |
||||
break; |
||||
} |
||||
|
||||
qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0; |
||||
|
||||
qh->data_toggle = DWC_OTG_HC_PID_DATA0; |
||||
qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe))); |
||||
INIT_LIST_HEAD(&qh->qtd_list); |
||||
INIT_LIST_HEAD(&qh->qh_list_entry); |
||||
qh->channel = NULL; |
||||
|
||||
/* FS/LS Enpoint on HS Hub
|
||||
* NOT virtual root hub */ |
||||
qh->do_split = 0; |
||||
if (((urb->dev->speed == USB_SPEED_LOW) || |
||||
(urb->dev->speed == USB_SPEED_FULL)) && |
||||
(urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1)) |
||||
{ |
||||
DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", |
||||
usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum, |
||||
urb->dev->ttport); |
||||
qh->do_split = 1; |
||||
} |
||||
|
||||
if (qh->ep_type == USB_ENDPOINT_XFER_INT || |
||||
qh->ep_type == USB_ENDPOINT_XFER_ISOC) { |
||||
/* Compute scheduling parameters once and save them. */ |
||||
hprt0_data_t hprt; |
||||
|
||||
/** @todo Account for split transfers in the bus time. */ |
||||
int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); |
||||
|
||||
/* FIXME: work-around patch by Steven */ |
||||
qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed, |
||||
usb_pipein(urb->pipe), |
||||
(qh->ep_type == USB_ENDPOINT_XFER_ISOC), |
||||
bytecount)); |
||||
|
||||
/* Start in a slightly future (micro)frame. */ |
||||
qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, |
||||
SCHEDULE_SLOP); |
||||
qh->interval = urb->interval; |
||||
#if 0 |
||||
/* Increase interrupt polling rate for debugging. */ |
||||
if (qh->ep_type == USB_ENDPOINT_XFER_INT) { |
||||
qh->interval = 8; |
||||
} |
||||
#endif |
||||
hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0); |
||||
if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && |
||||
((urb->dev->speed == USB_SPEED_LOW) || |
||||
(urb->dev->speed == USB_SPEED_FULL))) { |
||||
qh->interval *= 8; |
||||
qh->sched_frame |= 0x7; |
||||
qh->start_split_frame = qh->sched_frame; |
||||
} |
||||
|
||||
} |
||||
|
||||
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); |
||||
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh); |
||||
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", |
||||
urb->dev->devnum); |
||||
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", |
||||
usb_pipeendpoint(urb->pipe), |
||||
usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); |
||||
|
||||
switch(urb->dev->speed) { |
||||
case USB_SPEED_LOW: |
||||
speed = "low"; |
||||
break; |
||||
case USB_SPEED_FULL: |
||||
speed = "full"; |
||||
break; |
||||
case USB_SPEED_HIGH: |
||||
speed = "high"; |
||||
break; |
||||
default: |
||||
speed = "?"; |
||||
break; |
||||
} |
||||
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed); |
||||
|
||||
switch (qh->ep_type) { |
||||
case USB_ENDPOINT_XFER_ISOC: |
||||
type = "isochronous"; |
||||
break; |
||||
case USB_ENDPOINT_XFER_INT: |
||||
type = "interrupt"; |
||||
break; |
||||
case USB_ENDPOINT_XFER_CONTROL: |
||||
type = "control"; |
||||
break; |
||||
case USB_ENDPOINT_XFER_BULK: |
||||
type = "bulk"; |
||||
break; |
||||
default: |
||||
type = "?"; |
||||
break; |
||||
} |
||||
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type); |
||||
|
||||
#ifdef DEBUG |
||||
if (qh->ep_type == USB_ENDPOINT_XFER_INT) { |
||||
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", |
||||
qh->usecs); |
||||
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", |
||||
qh->interval); |
||||
} |
||||
#endif |
||||
qh->dw_align_buf = NULL; |
||||
return; |
||||
} |
||||
|
||||
/**
|
||||
* Checks that a channel is available for a periodic transfer. |
||||
* |
||||
* @return 0 if successful, negative error code otherise. |
||||
*/ |
||||
static int periodic_channel_available(dwc_otg_hcd_t *hcd) |
||||
{ |
||||
/*
|
||||
* Currently assuming that there is a dedicated host channnel for each |
||||
* periodic transaction plus at least one host channel for |
||||
* non-periodic transactions. |
||||
*/ |
||||
int status; |
||||
int num_channels; |
||||
|
||||
num_channels = hcd->core_if->core_params->host_channels; |
||||
if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) && |
||||
(hcd->periodic_channels < num_channels - 1)) { |
||||
status = 0; |
||||
} |
||||
else { |
||||
DWC_NOTICE("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", |
||||
__func__, num_channels, hcd->periodic_channels, |
||||
hcd->non_periodic_channels); |
||||
status = -ENOSPC; |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* Checks that there is sufficient bandwidth for the specified QH in the |
||||
* periodic schedule. For simplicity, this calculation assumes that all the |
||||
* transfers in the periodic schedule may occur in the same (micro)frame. |
||||
* |
||||
* @param hcd The HCD state structure for the DWC OTG controller. |
||||
* @param qh QH containing periodic bandwidth required. |
||||
* |
||||
* @return 0 if successful, negative error code otherwise. |
||||
*/ |
||||
static int check_periodic_bandwidth(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) |
||||
{ |
||||
int status; |
||||
uint16_t max_claimed_usecs; |
||||
|
||||
status = 0; |
||||
|
||||
if (hcd->core_if->core_params->speed == DWC_SPEED_PARAM_HIGH) { |
||||
/*
|
||||
* High speed mode. |
||||
* Max periodic usecs is 80% x 125 usec = 100 usec. |
||||
*/ |
||||
max_claimed_usecs = 100 - qh->usecs; |
||||
} else { |
||||
/*
|
||||
* Full speed mode. |
||||
* Max periodic usecs is 90% x 1000 usec = 900 usec. |
||||
*/ |
||||
max_claimed_usecs = 900 - qh->usecs; |
||||
} |
||||
|
||||
if (hcd->periodic_usecs > max_claimed_usecs) { |
||||
DWC_NOTICE("%s: already claimed usecs %d, required usecs %d\n", |
||||
__func__, hcd->periodic_usecs, qh->usecs); |
||||
status = -ENOSPC; |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* Checks that the max transfer size allowed in a host channel is large enough |
||||
* to handle the maximum data transfer in a single (micro)frame for a periodic |
||||
* transfer. |
||||
* |
||||
* @param hcd The HCD state structure for the DWC OTG controller. |
||||
* @param qh QH for a periodic endpoint. |
||||
* |
||||
* @return 0 if successful, negative error code otherwise. |
||||
*/ |
||||
static int check_max_xfer_size(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) |
||||
{ |
||||
int status; |
||||
uint32_t max_xfer_size; |
||||
uint32_t max_channel_xfer_size; |
||||
|
||||
status = 0; |
||||
|
||||
max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp); |
||||
max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size; |
||||
|
||||
if (max_xfer_size > max_channel_xfer_size) { |
||||
DWC_NOTICE("%s: Periodic xfer length %d > " |
||||
"max xfer length for channel %d\n", |
||||
__func__, max_xfer_size, max_channel_xfer_size); |
||||
status = -ENOSPC; |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* Schedules an interrupt or isochronous transfer in the periodic schedule. |
||||
* |
||||
* @param hcd The HCD state structure for the DWC OTG controller. |
||||
* @param qh QH for the periodic transfer. The QH should already contain the |
||||
* scheduling information. |
||||
* |
||||
* @return 0 if successful, negative error code otherwise. |
||||
*/ |
||||
static int schedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) |
||||
{ |
||||
int status = 0; |
||||
|
||||
status = periodic_channel_available(hcd); |
||||
if (status) { |
||||
DWC_NOTICE("%s: No host channel available for periodic " |
||||
"transfer.\n", __func__); |
||||
return status; |
||||
} |
||||
|
||||
status = check_periodic_bandwidth(hcd, qh); |
||||
if (status) { |
||||
DWC_NOTICE("%s: Insufficient periodic bandwidth for " |
||||
"periodic transfer.\n", __func__); |
||||
return status; |
||||
} |
||||
|
||||
status = check_max_xfer_size(hcd, qh); |
||||
if (status) { |
||||
DWC_NOTICE("%s: Channel max transfer size too small " |
||||
"for periodic transfer.\n", __func__); |
||||
return status; |
||||
} |
||||
|
||||
/* Always start in the inactive schedule. */ |
||||
list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive); |
||||
|
||||
/* Reserve the periodic channel. */ |
||||
hcd->periodic_channels++; |
||||
|
||||
/* Update claimed usecs per (micro)frame. */ |
||||
hcd->periodic_usecs += qh->usecs; |
||||
|
||||
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ |
||||
hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated += qh->usecs / qh->interval; |
||||
if (qh->ep_type == USB_ENDPOINT_XFER_INT) { |
||||
hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs++; |
||||
DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n", |
||||
qh, qh->usecs, qh->interval); |
||||
} else { |
||||
hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs++; |
||||
DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n", |
||||
qh, qh->usecs, qh->interval); |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* This function adds a QH to either the non periodic or periodic schedule if |
||||
* it is not already in the schedule. If the QH is already in the schedule, no |
||||
* action is taken. |
||||
* |
||||
* @return 0 if successful, negative error code otherwise. |
||||
*/ |
||||
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) |
||||
{ |
||||
unsigned long flags; |
||||
int status = 0; |
||||
|
||||
SPIN_LOCK_IRQSAVE(&hcd->lock, flags) |
||||
|
||||
if (!list_empty(&qh->qh_list_entry)) { |
||||
/* QH already in a schedule. */ |
||||
goto done; |
||||
} |
||||
|
||||
/* Add the new QH to the appropriate schedule */ |
||||
if (dwc_qh_is_non_per(qh)) { |
||||
/* Always start in the inactive schedule. */ |
||||
list_add_tail(&qh->qh_list_entry, &hcd->non_periodic_sched_inactive); |
||||
} else { |
||||
status = schedule_periodic(hcd, qh); |
||||
} |
||||
|
||||
done: |
||||
SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* Removes an interrupt or isochronous transfer from the periodic schedule. |
||||
* |
||||
* @param hcd The HCD state structure for the DWC OTG controller. |
||||
* @param qh QH for the periodic transfer. |
||||
*/ |
||||
static void deschedule_periodic(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) |
||||
{ |
||||
list_del_init(&qh->qh_list_entry); |
||||
|
||||
/* Release the periodic channel reservation. */ |
||||
hcd->periodic_channels--; |
||||
|
||||
/* Update claimed usecs per (micro)frame. */ |
||||
hcd->periodic_usecs -= qh->usecs; |
||||
|
||||
/* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ |
||||
hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_allocated -= qh->usecs / qh->interval; |
||||
|
||||
if (qh->ep_type == USB_ENDPOINT_XFER_INT) { |
||||
hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_int_reqs--; |
||||
DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n", |
||||
qh, qh->usecs, qh->interval); |
||||
} else { |
||||
hcd_to_bus(dwc_otg_hcd_to_hcd(hcd))->bandwidth_isoc_reqs--; |
||||
DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n", |
||||
qh, qh->usecs, qh->interval); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* Removes a QH from either the non-periodic or periodic schedule. Memory is |
||||
* not freed. |
||||
* |
||||
* @param[in] hcd The HCD state structure. |
||||
* @param[in] qh QH to remove from schedule. */ |
||||
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) |
||||
{ |
||||
unsigned long flags; |
||||
|
||||
SPIN_LOCK_IRQSAVE(&hcd->lock, flags); |
||||
|
||||
if (list_empty(&qh->qh_list_entry)) { |
||||
/* QH is not in a schedule. */ |
||||
goto done; |
||||
} |
||||
|
||||
if (dwc_qh_is_non_per(qh)) { |
||||
if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) { |
||||
hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; |
||||
} |
||||
list_del_init(&qh->qh_list_entry); |
||||
} else { |
||||
deschedule_periodic(hcd, qh); |
||||
} |
||||
|
||||
done: |
||||
SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags) |
||||
} |
||||
|
||||
/**
|
||||
* Deactivates a QH. For non-periodic QHs, removes the QH from the active |
||||
* non-periodic schedule. The QH is added to the inactive non-periodic |
||||
* schedule if any QTDs are still attached to the QH. |
||||
* |
||||
* For periodic QHs, the QH is removed from the periodic queued schedule. If |
||||
* there are any QTDs still attached to the QH, the QH is added to either the |
||||
* periodic inactive schedule or the periodic ready schedule and its next |
||||
* scheduled frame is calculated. The QH is placed in the ready schedule if |
||||
* the scheduled frame has been reached already. Otherwise it's placed in the |
||||
* inactive schedule. If there are no QTDs attached to the QH, the QH is |
||||
* completely removed from the periodic schedule. |
||||
*/ |
||||
void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split) |
||||
{ |
||||
unsigned long flags; |
||||
SPIN_LOCK_IRQSAVE(&hcd->lock, flags); |
||||
|
||||
if (dwc_qh_is_non_per(qh)) { |
||||
dwc_otg_hcd_qh_remove(hcd, qh); |
||||
if (!list_empty(&qh->qtd_list)) { |
||||
/* Add back to inactive non-periodic schedule. */ |
||||
dwc_otg_hcd_qh_add(hcd, qh); |
||||
} |
||||
} else { |
||||
uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd)); |
||||
|
||||
if (qh->do_split) { |
||||
/* Schedule the next continuing periodic split transfer */ |
||||
if (sched_next_periodic_split) { |
||||
|
||||
qh->sched_frame = frame_number; |
||||
if (dwc_frame_num_le(frame_number, |
||||
dwc_frame_num_inc(qh->start_split_frame, 1))) { |
||||
/*
|
||||
* Allow one frame to elapse after start |
||||
* split microframe before scheduling |
||||
* complete split, but DONT if we are |
||||
* doing the next start split in the |
||||
* same frame for an ISOC out. |
||||
*/ |
||||
if ((qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (qh->ep_is_in != 0)) { |
||||
qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, 1); |
||||
} |
||||
} |
||||
} else { |
||||
qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame, |
||||
qh->interval); |
||||
if (dwc_frame_num_le(qh->sched_frame, frame_number)) { |
||||
qh->sched_frame = frame_number; |
||||
} |
||||
qh->sched_frame |= 0x7; |
||||
qh->start_split_frame = qh->sched_frame; |
||||
} |
||||
} else { |
||||
qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval); |
||||
if (dwc_frame_num_le(qh->sched_frame, frame_number)) { |
||||
qh->sched_frame = frame_number; |
||||
} |
||||
} |
||||
|
||||
if (list_empty(&qh->qtd_list)) { |
||||
dwc_otg_hcd_qh_remove(hcd, qh); |
||||
} else { |
||||
/*
|
||||
* Remove from periodic_sched_queued and move to |
||||
* appropriate queue. |
||||
*/ |
||||
if (qh->sched_frame == frame_number) { |
||||
list_move(&qh->qh_list_entry, |
||||
&hcd->periodic_sched_ready); |
||||
} else { |
||||
list_move(&qh->qh_list_entry, |
||||
&hcd->periodic_sched_inactive); |
||||
} |
||||
} |
||||
} |
||||
|
||||
SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags); |
||||
} |
||||
|
||||
/**
|
||||
* This function allocates and initializes a QTD. |
||||
* |
||||
* @param[in] urb The URB to create a QTD from. Each URB-QTD pair will end up |
||||
* pointing to each other so each pair should have a unique correlation. |
||||
* |
||||
* @return Returns pointer to the newly allocated QTD, or NULL on error. */ |
||||
dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb) |
||||
{ |
||||
dwc_otg_qtd_t *qtd; |
||||
|
||||
qtd = dwc_otg_hcd_qtd_alloc (); |
||||
if (qtd == NULL) { |
||||
return NULL; |
||||
} |
||||
|
||||
dwc_otg_hcd_qtd_init (qtd, urb); |
||||
return qtd; |
||||
} |
||||
|
||||
/**
|
||||
* Initializes a QTD structure. |
||||
* |
||||
* @param[in] qtd The QTD to initialize. |
||||
* @param[in] urb The URB to use for initialization. */ |
||||
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb) |
||||
{ |
||||
memset (qtd, 0, sizeof (dwc_otg_qtd_t)); |
||||
qtd->urb = urb; |
||||
if (usb_pipecontrol(urb->pipe)) { |
||||
/*
|
||||
* The only time the QTD data toggle is used is on the data |
||||
* phase of control transfers. This phase always starts with |
||||
* DATA1. |
||||
*/ |
||||
qtd->data_toggle = DWC_OTG_HC_PID_DATA1; |
||||
qtd->control_phase = DWC_OTG_CONTROL_SETUP; |
||||
} |
||||
|
||||
/* start split */ |
||||
qtd->complete_split = 0; |
||||
qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; |
||||
qtd->isoc_split_offset = 0; |
||||
|
||||
/* Store the qtd ptr in the urb to reference what QTD. */ |
||||
urb->hcpriv = qtd; |
||||
return; |
||||
} |
||||
|
||||
/**
|
||||
* This function adds a QTD to the QTD-list of a QH. It will find the correct |
||||
* QH to place the QTD into. If it does not find a QH, then it will create a |
||||
* new QH. If the QH to which the QTD is added is not currently scheduled, it |
||||
* is placed into the proper schedule based on its EP type. |
||||
* |
||||
* @param[in] qtd The QTD to add |
||||
* @param[in] dwc_otg_hcd The DWC HCD structure |
||||
* |
||||
* @return 0 if successful, negative error code otherwise. |
||||
*/ |
||||
int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, |
||||
dwc_otg_hcd_t *dwc_otg_hcd) |
||||
{ |
||||
struct usb_host_endpoint *ep; |
||||
dwc_otg_qh_t *qh; |
||||
unsigned long flags; |
||||
int retval = 0; |
||||
|
||||
struct urb *urb = qtd->urb; |
||||
|
||||
SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags); |
||||
|
||||
/*
|
||||
* Get the QH which holds the QTD-list to insert to. Create QH if it |
||||
* doesn't exist. |
||||
*/ |
||||
ep = dwc_urb_to_endpoint(urb); |
||||
qh = (dwc_otg_qh_t *)ep->hcpriv; |
||||
if (qh == NULL) { |
||||
qh = dwc_otg_hcd_qh_create (dwc_otg_hcd, urb); |
||||
if (qh == NULL) { |
||||
goto done; |
||||
} |
||||
ep->hcpriv = qh; |
||||
} |
||||
|
||||
retval = dwc_otg_hcd_qh_add(dwc_otg_hcd, qh); |
||||
if (retval == 0) { |
||||
list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); |
||||
} |
||||
|
||||
done: |
||||
SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags); |
||||
|
||||
return retval; |
||||
} |
||||
|
||||
#endif /* DWC_DEVICE_ONLY */ |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,244 @@ |
||||
/* ==========================================================================
|
||||
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
|
||||
* $Revision: 1.2 $ |
||||
* $Date: 2008-11-21 05:39:15 $ |
||||
* $Change: 1103515 $ |
||||
* |
||||
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
||||
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
||||
* otherwise expressly agreed to in writing between Synopsys and you. |
||||
* |
||||
* The Software IS NOT an item of Licensed Software or Licensed Product under |
||||
* any End User Software License Agreement or Agreement for Licensed Product |
||||
* with Synopsys or any supplement thereto. You are permitted to use and |
||||
* redistribute this Software in source and binary forms, with or without |
||||
* modification, provided that redistributions of source code must retain this |
||||
* notice. You may not view, use, disclose, copy or distribute this file or |
||||
* any information contained herein except pursuant to this license grant from |
||||
* Synopsys. If you do not agree with this notice, including the disclaimer |
||||
* below, then you are not authorized to use the Software. |
||||
* |
||||
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
||||
* DAMAGE. |
||||
* ========================================================================== */ |
||||
#ifndef DWC_HOST_ONLY |
||||
#if !defined(__DWC_PCD_H__) |
||||
#define __DWC_PCD_H__ |
||||
|
||||
#include <linux/types.h> |
||||
#include <linux/list.h> |
||||
#include <linux/errno.h> |
||||
#include <linux/device.h> |
||||
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) |
||||
# include <linux/usb/ch9.h> |
||||
#else |
||||
# include <linux/usb_ch9.h> |
||||
#endif |
||||
|
||||
#include <linux/usb_gadget.h> |
||||
#include <linux/interrupt.h> |
||||
#include <linux/dma-mapping.h> |
||||
|
||||
struct dwc_otg_device; |
||||
|
||||
#include "dwc_otg_cil.h" |
||||
|
||||
/**
|
||||
* @file |
||||
* |
||||
* This file contains the structures, constants, and interfaces for |
||||
* the Perpherial Contoller Driver (PCD). |
||||
* |
||||
* The Peripheral Controller Driver (PCD) for Linux will implement the |
||||
* Gadget API, so that the existing Gadget drivers can be used. For |
||||
* the Mass Storage Function driver the File-backed USB Storage Gadget |
||||
* (FBS) driver will be used. The FBS driver supports the |
||||
* Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only |
||||
* transports. |
||||
* |
||||
*/ |
||||
|
||||
/** Invalid DMA Address */ |
||||
#define DMA_ADDR_INVALID (~(dma_addr_t)0) |
||||
/** Maxpacket size for EP0 */ |
||||
#define MAX_EP0_SIZE 64 |
||||
/** Maxpacket size for any EP */ |
||||
#define MAX_PACKET_SIZE 1024 |
||||
|
||||
/** Max Transfer size for any EP */ |
||||
#define MAX_TRANSFER_SIZE 65535 |
||||
|
||||
/** Max DMA Descriptor count for any EP */ |
||||
#define MAX_DMA_DESC_CNT 64 |
||||
|
||||
/**
|
||||
* Get the pointer to the core_if from the pcd pointer. |
||||
*/ |
||||
#define GET_CORE_IF( _pcd ) (_pcd->otg_dev->core_if) |
||||
|
||||
/**
|
||||
* States of EP0. |
||||
*/ |
||||
typedef enum ep0_state |
||||
{ |
||||
EP0_DISCONNECT, /* no host */ |
||||
EP0_IDLE, |
||||
EP0_IN_DATA_PHASE, |
||||
EP0_OUT_DATA_PHASE, |
||||
EP0_IN_STATUS_PHASE, |
||||
EP0_OUT_STATUS_PHASE, |
||||
EP0_STALL, |
||||
} ep0state_e; |
||||
|
||||
/** Fordward declaration.*/ |
||||
struct dwc_otg_pcd; |
||||
|
||||
/** DWC_otg iso request structure.
|
||||
* |
||||
*/ |
||||
typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; |
||||
|
||||
/** PCD EP structure.
|
||||
* This structure describes an EP, there is an array of EPs in the PCD |
||||
* structure. |
||||
*/ |
||||
typedef struct dwc_otg_pcd_ep |
||||
{ |
||||
/** USB EP data */ |
||||
struct usb_ep ep; |
||||
/** USB EP Descriptor */ |
||||
const struct usb_endpoint_descriptor *desc; |
||||
|
||||
/** queue of dwc_otg_pcd_requests. */ |
||||
struct list_head queue; |
||||
unsigned stopped : 1; |
||||
unsigned disabling : 1; |
||||
unsigned dma : 1; |
||||
unsigned queue_sof : 1; |
||||
|
||||
#ifdef DWC_EN_ISOC |
||||
/** DWC_otg Isochronous Transfer */ |
||||
struct usb_iso_request* iso_req; |
||||
#endif //DWC_EN_ISOC
|
||||
|
||||
/** DWC_otg ep data. */ |
||||
dwc_ep_t dwc_ep; |
||||
|
||||
/** Pointer to PCD */ |
||||
struct dwc_otg_pcd *pcd; |
||||
}dwc_otg_pcd_ep_t; |
||||
|
||||
|
||||
|
||||
/** DWC_otg PCD Structure.
|
||||
* This structure encapsulates the data for the dwc_otg PCD. |
||||
*/ |
||||
typedef struct dwc_otg_pcd |
||||
{ |
||||
/** USB gadget */ |
||||
struct usb_gadget gadget; |
||||
/** USB gadget driver pointer*/ |
||||
struct usb_gadget_driver *driver; |
||||
/** The DWC otg device pointer. */ |
||||
struct dwc_otg_device *otg_dev; |
||||
|
||||
/** State of EP0 */ |
||||
ep0state_e ep0state; |
||||
/** EP0 Request is pending */ |
||||
unsigned ep0_pending : 1; |
||||
/** Indicates when SET CONFIGURATION Request is in process */ |
||||
unsigned request_config : 1; |
||||
/** The state of the Remote Wakeup Enable. */ |
||||
unsigned remote_wakeup_enable : 1; |
||||
/** The state of the B-Device HNP Enable. */ |
||||
unsigned b_hnp_enable : 1; |
||||
/** The state of A-Device HNP Support. */ |
||||
unsigned a_hnp_support : 1; |
||||
/** The state of the A-Device Alt HNP support. */ |
||||
unsigned a_alt_hnp_support : 1; |
||||
/** Count of pending Requests */ |
||||
unsigned request_pending; |
||||
|
||||
/** SETUP packet for EP0
|
||||
* This structure is allocated as a DMA buffer on PCD initialization |
||||
* with enough space for up to 3 setup packets. |
||||
*/ |
||||
union |
||||
{ |
||||
struct usb_ctrlrequest req; |
||||
uint32_t d32[2]; |
||||
} *setup_pkt; |
||||
|
||||
dma_addr_t setup_pkt_dma_handle; |
||||
|
||||
/** 2-byte dma buffer used to return status from GET_STATUS */ |
||||
uint16_t *status_buf; |
||||
dma_addr_t status_buf_dma_handle; |
||||
|
||||
/** EP0 */ |
||||
dwc_otg_pcd_ep_t ep0; |
||||
|
||||
/** Array of IN EPs. */ |
||||
dwc_otg_pcd_ep_t in_ep[ MAX_EPS_CHANNELS - 1]; |
||||
/** Array of OUT EPs. */ |
||||
dwc_otg_pcd_ep_t out_ep[ MAX_EPS_CHANNELS - 1]; |
||||
/** number of valid EPs in the above array. */ |
||||
// unsigned num_eps : 4;
|
||||
spinlock_t lock; |
||||
/** Timer for SRP. If it expires before SRP is successful
|
||||
* clear the SRP. */ |
||||
struct timer_list srp_timer; |
||||
|
||||
/** Tasklet to defer starting of TEST mode transmissions until
|
||||
* Status Phase has been completed. |
||||
*/ |
||||
struct tasklet_struct test_mode_tasklet; |
||||
|
||||
/** Tasklet to delay starting of xfer in DMA mode */ |
||||
struct tasklet_struct *start_xfer_tasklet; |
||||
|
||||
/** The test mode to enter when the tasklet is executed. */ |
||||
unsigned test_mode; |
||||
|
||||
} dwc_otg_pcd_t; |
||||
|
||||
|
||||
/** DWC_otg request structure.
|
||||
* This structure is a list of requests. |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
struct usb_request req; /**< USB Request. */ |
||||
struct list_head queue; /**< queue of these requests. */ |
||||
} dwc_otg_pcd_request_t; |
||||
|
||||
|
||||
extern int dwc_otg_pcd_init(struct device *dev); |
||||
|
||||
//extern void dwc_otg_pcd_remove( struct dwc_otg_device *_otg_dev );
|
||||
extern void dwc_otg_pcd_remove( struct device *dev); |
||||
extern int32_t dwc_otg_pcd_handle_intr( dwc_otg_pcd_t *pcd ); |
||||
extern void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t *pcd ); |
||||
|
||||
extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t *pcd); |
||||
extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t *pcd, int set); |
||||
|
||||
extern void dwc_otg_iso_buffer_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_iso_request_t *req); |
||||
extern void dwc_otg_request_done(dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *req, |
||||
int status); |
||||
extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *_ep); |
||||
extern void dwc_otg_pcd_update_otg(dwc_otg_pcd_t *_pcd, |
||||
const unsigned reset); |
||||
|
||||
#endif |
||||
#endif /* DWC_HOST_ONLY */ |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,260 @@ |
||||
/* ==========================================================================
|
||||
* $File: //dwh/usb_iip/dev/software/otg/linux/platform/dwc_otg_plat.h $
|
||||
* $Revision: 1.2 $ |
||||
* $Date: 2008-11-21 05:39:16 $ |
||||
* $Change: 1064915 $ |
||||
* |
||||
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter, |
||||
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless |
||||
* otherwise expressly agreed to in writing between Synopsys and you. |
||||
* |
||||
* The Software IS NOT an item of Licensed Software or Licensed Product under |
||||
* any End User Software License Agreement or Agreement for Licensed Product |
||||
* with Synopsys or any supplement thereto. You are permitted to use and |
||||
* redistribute this Software in source and binary forms, with or without |
||||
* modification, provided that redistributions of source code must retain this |
||||
* notice. You may not view, use, disclose, copy or distribute this file or |
||||
* any information contained herein except pursuant to this license grant from |
||||
* Synopsys. If you do not agree with this notice, including the disclaimer |
||||
* below, then you are not authorized to use the Software. |
||||
* |
||||
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, |
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
||||
* DAMAGE. |
||||
* ========================================================================== */ |
||||
|
||||
#if !defined(__DWC_OTG_PLAT_H__) |
||||
#define __DWC_OTG_PLAT_H__ |
||||
|
||||
#include <linux/types.h> |
||||
#include <linux/slab.h> |
||||
#include <linux/list.h> |
||||
#include <linux/delay.h> |
||||
#include <asm/io.h> |
||||
|
||||
/**
|
||||
* @file |
||||
* |
||||
* This file contains the Platform Specific constants, interfaces |
||||
* (functions and macros) for Linux. |
||||
* |
||||
*/ |
||||
//#if !defined(__LINUX_ARM_ARCH__)
|
||||
//#error "The contents of this file is Linux specific!!!"
|
||||
//#endif
|
||||
|
||||
/**
|
||||
* Reads the content of a register. |
||||
* |
||||
* @param reg address of register to read. |
||||
* @return contents of the register. |
||||
* |
||||
|
||||
* Usage:<br> |
||||
* <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code> |
||||
*/ |
||||
static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *reg) |
||||
{ |
||||
return readl(reg); |
||||
}; |
||||
|
||||
/**
|
||||
* Writes a register with a 32 bit value. |
||||
* |
||||
* @param reg address of register to read. |
||||
* @param value to write to _reg. |
||||
* |
||||
* Usage:<br> |
||||
* <code>dwc_write_reg32(&dev_regs->dctl, 0); </code> |
||||
*/ |
||||
static __inline__ void dwc_write_reg32( volatile uint32_t *reg, const uint32_t value) |
||||
{ |
||||
writel( value, reg ); |
||||
}; |
||||
|
||||
/**
|
||||
* This function modifies bit values in a register. Using the |
||||
* algorithm: (reg_contents & ~clear_mask) | set_mask. |
||||
* |
||||
* @param reg address of register to read. |
||||
* @param clear_mask bit mask to be cleared. |
||||
* @param set_mask bit mask to be set. |
||||
* |
||||
* Usage:<br> |
||||
* <code> // Clear the SOF Interrupt Mask bit and <br>
|
||||
* // set the OTG Interrupt mask bit, leaving all others as they were.
|
||||
* dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code> |
||||
*/ |
||||
static __inline__ |
||||
void dwc_modify_reg32( volatile uint32_t *reg, const uint32_t clear_mask, const uint32_t set_mask) |
||||
{ |
||||
writel( (readl(reg) & ~clear_mask) | set_mask, reg ); |
||||
}; |
||||
|
||||
|
||||
/**
|
||||
* Wrapper for the OS micro-second delay function. |
||||
* @param[in] usecs Microseconds of delay |
||||
*/ |
||||
static __inline__ void UDELAY( const uint32_t usecs ) |
||||
{ |
||||
udelay( usecs ); |
||||
} |
||||
|
||||
/**
|
||||
* Wrapper for the OS milli-second delay function. |
||||
* @param[in] msecs milliseconds of delay |
||||
*/ |
||||
static __inline__ void MDELAY( const uint32_t msecs ) |
||||
{ |
||||
mdelay( msecs ); |
||||
} |
||||
|
||||
/**
|
||||
* Wrapper for the Linux spin_lock. On the ARM (Integrator) |
||||
* spin_lock() is a nop. |
||||
* |
||||
* @param lock Pointer to the spinlock. |
||||
*/ |
||||
static __inline__ void SPIN_LOCK( spinlock_t *lock ) |
||||
{ |
||||
spin_lock(lock); |
||||
} |
||||
|
||||
/**
|
||||
* Wrapper for the Linux spin_unlock. On the ARM (Integrator) |
||||
* spin_lock() is a nop. |
||||
* |
||||
* @param lock Pointer to the spinlock. |
||||
*/ |
||||
static __inline__ void SPIN_UNLOCK( spinlock_t *lock ) |
||||
{ |
||||
spin_unlock(lock); |
||||
} |
||||
|
||||
/**
|
||||
* Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM |
||||
* (Integrator) spin_lock() is a nop. |
||||
* |
||||
* @param l Pointer to the spinlock. |
||||
* @param f unsigned long for irq flags storage. |
||||
*/ |
||||
#define SPIN_LOCK_IRQSAVE( l, f ) spin_lock_irqsave(l,f); |
||||
|
||||
/**
|
||||
* Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM |
||||
* (Integrator) spin_lock() is a nop. |
||||
* |
||||
* @param l Pointer to the spinlock. |
||||
* @param f unsigned long for irq flags storage. |
||||
*/ |
||||
#define SPIN_UNLOCK_IRQRESTORE( l,f ) spin_unlock_irqrestore(l,f); |
||||
|
||||
/*
|
||||
* Debugging support vanishes in non-debug builds. |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* The Debug Level bit-mask variable. |
||||
*/ |
||||
extern uint32_t g_dbg_lvl; |
||||
/**
|
||||
* Set the Debug Level variable. |
||||
*/ |
||||
static inline uint32_t SET_DEBUG_LEVEL( const uint32_t new ) |
||||
{ |
||||
uint32_t old = g_dbg_lvl; |
||||
g_dbg_lvl = new; |
||||
return old; |
||||
} |
||||
|
||||
/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ |
||||
#define DBG_CIL (0x2) |
||||
/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
|
||||
* messages */ |
||||
#define DBG_CILV (0x20) |
||||
/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
|
||||
* messages */ |
||||
#define DBG_PCD (0x4) |
||||
/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
|
||||
* messages */ |
||||
#define DBG_PCDV (0x40) |
||||
/** When debug level has the DBG_HCD bit set, display Host debug messages */ |
||||
#define DBG_HCD (0x8) |
||||
/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
|
||||
* messages */ |
||||
#define DBG_HCDV (0x80) |
||||
/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
|
||||
* mode. */ |
||||
#define DBG_HCD_URB (0x800) |
||||
|
||||
/** When debug level has any bit set, display debug messages */ |
||||
#define DBG_ANY (0xFF) |
||||
|
||||
/** All debug messages off */ |
||||
#define DBG_OFF 0 |
||||
|
||||
/** Prefix string for DWC_DEBUG print macros. */ |
||||
#define USB_DWC "dwc_otg: " |
||||
|
||||
/**
|
||||
* Print a debug message when the Global debug level variable contains |
||||
* the bit defined in <code>lvl</code>. |
||||
* |
||||
* @param[in] lvl - Debug level, use one of the DBG_ constants above. |
||||
* @param[in] x - like printf |
||||
* |
||||
* Example:<p> |
||||
* <code> |
||||
* DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); |
||||
* </code> |
||||
* <br> |
||||
* results in:<br> |
||||
* <code> |
||||
* usb-DWC_otg: dwc_otg_cil_init(ca867000) |
||||
* </code> |
||||
*/ |
||||
#ifdef DEBUG |
||||
|
||||
# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0) |
||||
# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) |
||||
|
||||
# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) |
||||
|
||||
#else |
||||
|
||||
# define DWC_DEBUGPL(lvl, x...) do{}while(0) |
||||
# define DWC_DEBUGP(x...) |
||||
|
||||
# define CHK_DEBUG_LEVEL(level) (0) |
||||
|
||||
#endif /*DEBUG*/ |
||||
|
||||
/**
|
||||
* Print an Error message. |
||||
*/ |
||||
#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x ) |
||||
/**
|
||||
* Print a Warning message. |
||||
*/ |
||||
#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x ) |
||||
/**
|
||||
* Print a notice (normal but significant message). |
||||
*/ |
||||
#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x ) |
||||
/**
|
||||
* Basic message printing. |
||||
*/ |
||||
#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x ) |
||||
|
||||
#endif |
||||
|
@ -0,0 +1,16 @@ |
||||
--- a/drivers/usb/Kconfig
|
||||
+++ b/drivers/usb/Kconfig
|
||||
@@ -163,4 +163,6 @@
|
||||
|
||||
source "drivers/usb/otg/Kconfig"
|
||||
|
||||
+source "drivers/usb/dwc_otg/Kconfig"
|
||||
+
|
||||
endif # USB_SUPPORT
|
||||
--- a/drivers/usb/Makefile
|
||||
+++ b/drivers/usb/Makefile
|
||||
@@ -45,3 +45,4 @@
|
||||
|
||||
obj-$(CONFIG_USB_ATM) += atm/
|
||||
obj-$(CONFIG_USB_SPEEDTOUCH) += atm/
|
||||
+obj-$(CONFIG_DWC_OTG) += dwc_otg/
|
Loading…
Reference in new issue