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From 4fd286c3e5a5bebab0391cf1937695b3ed6721a3 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 30 Nov 2014 20:20:30 +0100
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Subject: [PATCH 4/5] MIPS: BCM63XX: wire up BCM6358's external interrupts 4
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and 5
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Due to the external interrupts being non consecutive, the previous
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implementation did not support them. Now that we treat both registers
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as separate irq controllers, there is no such limitation anymore and
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we can expose them for drivers to use.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 5 ++++-
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 ++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 +
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3 files changed, 7 insertions(+), 1 deletion(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -109,11 +109,14 @@ static void bcm63xx_init_irq(void)
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periph_width = 1;
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ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
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- ext_irq_count = 4;
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+ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6358;
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+ ext_irq_count = 6;
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ext_irqs[0] = BCM_6358_EXT_IRQ0;
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ext_irqs[1] = BCM_6358_EXT_IRQ1;
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ext_irqs[2] = BCM_6358_EXT_IRQ2;
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ext_irqs[3] = BCM_6358_EXT_IRQ3;
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+ ext_irqs[4] = BCM_6358_EXT_IRQ4;
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+ ext_irqs[5] = BCM_6358_EXT_IRQ5;
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ext_shift = 4;
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break;
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case BCM6362_CPU_ID:
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -895,6 +895,8 @@ enum bcm63xx_irq {
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#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
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#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
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#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
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+#define BCM_6358_EXT_IRQ4 (IRQ_INTERNAL_BASE + 20)
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+#define BCM_6358_EXT_IRQ5 (IRQ_INTERNAL_BASE + 21)
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/*
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* 6362 irqs
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -243,6 +243,7 @@
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#define PERF_EXTIRQ_CFG_REG_6362 0x18
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#define PERF_EXTIRQ_CFG_REG_6368 0x18
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+#define PERF_EXTIRQ_CFG_REG2_6358 0x1c
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#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
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/* for 6348 only */
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