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@ -1,47 +1,72 @@ |
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From 4d3886359d6f6ac475e143d5f3e3b389542a0510 Mon Sep 17 00:00:00 2001
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From 7aaa70416d87434792b73077beb328202975e541 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 30 Nov 2014 14:53:12 +0100
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Subject: [PATCH 17/20] irqchip: add support for bcm6345-style l2 irq
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Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq
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controller
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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.../interrupt-controller/brcm,bcm6345-l2-intc.txt | 25 ++
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.../brcm,bcm6345-periph-intc.txt | 50 +++
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drivers/irqchip/Kconfig | 4 +
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drivers/irqchip/Makefile | 1 +
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drivers/irqchip/irq-bcm6345-l2.c | 320 ++++++++++++++++++++
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include/linux/irqchip/irq-bcm6345-l2-intc.h | 16 +
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5 files changed, 366 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
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create mode 100644 drivers/irqchip/irq-bcm6345-l2.c
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create mode 100644 include/linux/irqchip/irq-bcm6345-l2-intc.h
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drivers/irqchip/irq-bcm6345-periph.c | 325 ++++++++++++++++++++
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include/linux/irqchip/irq-bcm6345-periph.h | 16 +
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5 files changed, 396 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
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create mode 100644 drivers/irqchip/irq-bcm6345-periph.c
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create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
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@@ -0,0 +1,25 @@
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+Broadcom BCM6345 Level 2 interrupt controller
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+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
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@@ -0,0 +1,50 @@
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+Broadcom BCM6345 Level 1 periphery interrupt controller
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+
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+This block is a interrupt controller that is typically connected directly
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+to one of the HW INT lines on each CPU. Every BCM63XX xDSL chip since
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+BCM6345 has contained this hardware.
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+
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+Key elements of the hardware design include:
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+
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+- 32, 64, or 128 incoming level IRQ lines
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+
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+- All onchip peripherals are wired directly to an L2 input
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+
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+- A separate instance of the register set for each CPU, allowing individual
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+ peripheral IRQs to be routed to any CPU
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+
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+- No atomic mask/unmask operations
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+
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+- No polarity/level/edge settings
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+
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+- No FIFO or priority encoder logic; software is expected to read all
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+ 1-4 status words to determine which IRQs are pending
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+
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+Required properties:
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+
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+- compatible: should be "brcm,bcm6345-l2-intc"
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+- reg: specifies the base physical address and size of the registers;
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+ multiple regs may be specified, and must match the amount of parent interrupts
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+- interrupt-controller: identifies the node as an interrupt controller
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+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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+ source, should be 1
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+- interrupt-parent: specifies the phandle to the parent interrupt controller
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+ this one is cascaded from
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+- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
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+ node, valid values depend on the type of parent interrupt controller
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+- compatible: Should be "brcm,bcm6345-periph-intc".
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+- reg: Specifies the base physical address and size of the registers.
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+ Multiple register addresses may be specified, and must match the amount of
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+ parent interrupts.
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+- interrupt-controller: Identifies the node as an interrupt controller.
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+- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
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+ source, should be 1.
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+- interrupt-parent: Specifies the phandle to the parent interrupt controller
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+ this one is cascaded from.
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+- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
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+ node, valid values depend on the type of parent interrupt controller.
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+ Multiple lines are used to route interrupts to different cpus, with the first
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+ assumed to be for the boot CPU.
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+
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+Example:
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+
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+periph_intc: interrupt-controller@f0406800 {
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+ compatible = "brcm,bcm6345-l2-intc";
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+ interrupt-parent = <&mips_intc>;
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+ #interrupt-cells = <1>;
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+ reg = <0x10000020 0x10> <0x10000030 0x10>;
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+ compatible = "brcm,bcm6345-periph-intc";
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+ reg = <0x10000020 0x10>, <0x10000030 0x10>;
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+
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ interrupt-parent = <&cpu_intc>;
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+ interrupts = <2>, <3>;
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+};
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--- a/drivers/irqchip/Kconfig
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@ -50,7 +75,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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The maximum number of VICs available in the system, for
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power management.
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+config BCM6345_L2_IRQ
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+config BCM6345_PERIPH_IRQ
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+ bool
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+ select IRQ_DOMAIN
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+
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@ -63,13 +88,13 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
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obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
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obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
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+obj-$(CONFIG_BCM6345_L2_IRQ) += irq-bcm6345-l2.o
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+obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
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obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
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obj-$(CONFIG_METAG) += irq-metag-ext.o
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obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
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--- /dev/null
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+++ b/drivers/irqchip/irq-bcm6345-l2.c
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@@ -0,0 +1,320 @@
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+++ b/drivers/irqchip/irq-bcm6345-periph.c
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@@ -0,0 +1,340 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -81,7 +106,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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+#include <linux/ioport.h>
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+#include <linux/irq.h>
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+#include <linux/irqchip/chained_irq.h>
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+#include <linux/irqchip/irq-bcm6345-l2-intc.h>
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+#include <linux/irqchip/irq-bcm6345-periph.h>
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+#include <linux/kernel.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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@ -118,10 +143,10 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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+ int num_words;
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+
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+ struct irq_domain *domain;
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+ spinlock_t lock;
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+ raw_spinlock_t lock;
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+};
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+
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+static void bcm6345_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
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+static void bcm6345_periph_irq_handle(unsigned int irq, struct irq_desc *desc)
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+{
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+ struct intc_data *data = irq_desc_get_handler_data(desc);
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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@ -139,20 +164,36 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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+ unsigned long pending;
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+ int hw_irq;
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+
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+ raw_spin_lock(data->lock);
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+ raw_spin_lock(&data->lock);
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+ pending = __raw_readl(block->en_reg[idx]) &
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+ __raw_readl(block->status_reg[idx]);
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+ raw_spin_unlock(data->lock);
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+ raw_spin_unlock(&data->lock);
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+
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+ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
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+ generic_handle_irq(irq_find_mapping(data->domain, base + hw_irq));
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+ int virq;
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+
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+ virq = irq_find_mapping(data->domain, base + hw_irq);
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+ generic_handle_irq(virq);
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+ }
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+ }
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+
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+ chained_irq_exit(chip, desc);
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+}
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+
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+static void bcm6345_l2_intc_irq_mask(struct irq_data *data)
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+static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,
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+ bool enable)
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+{
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+ u32 val;
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+
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+ val = __raw_readl(block->en_reg[reg]);
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+ if (enable)
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+ val |= BIT(bit);
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+ else
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+ val &= ~BIT(bit);
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+ __raw_writel(val, block->en_reg[reg]);
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+}
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+
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+static void bcm6345_periph_irq_mask(struct irq_data *data)
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+{
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+ unsigned int i, reg, bit;
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+ struct intc_data *priv = data->domain->host_data;
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@ -161,58 +202,51 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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+ reg = hwirq / IRQS_PER_WORD;
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+ bit = hwirq % IRQS_PER_WORD;
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+
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+ raw_spin_lock(priv->lock);
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+ raw_spin_lock(&priv->lock);
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+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
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+ struct intc_block *block = &priv->block[i];
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+ u32 val;
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+
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+ if (!block->parent_irq)
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+ break;
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+
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+ val = __raw_readl(block->en_reg[reg]);
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+ __raw_writel(val & ~BIT(bit), block->en_reg[reg]);
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+ __bcm6345_periph_enable(block, reg, bit, false);
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+ }
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+ raw_spin_unlock(priv->lock);
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+ raw_spin_unlock(&priv->lock);
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+}
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+
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+static void bcm6345_l2_intc_irq_unmask(struct irq_data *data)
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+static void bcm6345_periph_irq_unmask(struct irq_data *data)
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+{
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+ unsigned int i, reg, bit;
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+ struct intc_data *priv = data->domain->host_data;
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+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
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+ unsigned int i, reg, bit;
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+
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+ reg = hwirq / IRQS_PER_WORD;
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+ bit = hwirq % IRQS_PER_WORD;
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+
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+ raw_spin_lock(priv->lock);
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+ raw_spin_lock(&priv->lock);
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+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
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+ struct intc_block *block = &priv->block[i];
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+ u32 val;
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+
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+ if (!block->parent_irq)
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+ break;
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+
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+ val = __raw_readl(block->en_reg[reg]);
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+
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+ if (block->mask_cache[reg] & BIT(bit))
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+ val |= BIT(bit);
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+ __bcm6345_periph_enable(block, reg, bit, true);
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+ else
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+ val &= ~BIT(bit);
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+
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+ __raw_writel(val, block->en_reg[reg]);
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+ __bcm6345_periph_enable(block, reg, bit, false);
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+
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+ }
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+ raw_spin_unlock(priv->lock);
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+ raw_spin_unlock(&priv->lock);
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+}
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+
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+#ifdef CONFIG_SMP
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+static int bcm6345_l2_intc_set_affinity(struct irq_data *data,
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+ const struct cpumask *mask,
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+ bool force)
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+static int bcm6345_periph_set_affinity(struct irq_data *data,
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+ const struct cpumask *mask, bool force)
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+{
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+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
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+ struct intc_data *priv = data->domain->host_data;
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+ unsigned int i, reg, bit;
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+ bool enabled;
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+ int cpu;
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+
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+ reg = hwirq / IRQS_PER_WORD;
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@ -231,21 +265,30 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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+ if (!priv->block[cpu].parent_irq)
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+ return -EINVAL;
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+
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+ raw_spin_lock(priv->lock);
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+ raw_spin_lock(&priv->lock);
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+ enabled = !irqd_irq_masked(data);
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+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
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+ if (i == cpu)
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+ priv->block[i].mask_cache[reg] |= BIT(bit);
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+ else
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+ priv->block[i].mask_cache[reg] &= ~BIT(bit);
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+ struct intc_block *block = &priv->block[i];
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+
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+ if (!block->parent_irq)
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+ break;
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+
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+ if (i == cpu) {
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+ block->mask_cache[reg] |= BIT(bit);
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+ __bcm6345_periph_enable(block, reg, bit, enabled);
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+ } else {
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+ block->mask_cache[reg] &= ~BIT(bit);
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+ __bcm6345_periph_enable(block, reg, bit, false);
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+ }
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+ }
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+ raw_spin_unlock(priv->lock);
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+ raw_spin_unlock(&priv->lock);
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+
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+ return 0;
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+}
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+#endif
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+
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+static int bcm6345_l2_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+{
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+ struct intc_data *priv = d->host_data;
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+
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@ -254,14 +297,14 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops bcm6345_l2_domain_ops = {
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+static const struct irq_domain_ops bcm6345_periph_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = bcm6345_l2_map,
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+ .map = bcm6345_periph_map,
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+};
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+
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+static int __init __bcm6345_l2_intc_init(struct device_node *node,
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+ int num_blocks, int *irq,
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+ void __iomem **base, int num_words)
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+static int __init __bcm6345_periph_intc_init(struct device_node *node,
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+ int num_blocks, int *irq,
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+ void __iomem **base, int num_words)
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+{
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+ struct intc_data *data;
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+ unsigned int i, w, status_offset;
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@ -270,6 +313,8 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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+ if (!data)
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+ return -ENOMEM;
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+
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+ raw_spin_lock_init(&data->lock);
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+
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+ status_offset = num_words * sizeof(u32);
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+
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|
+ for (i = 0; i < num_blocks; i++) {
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|
@ -292,23 +337,23 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
|
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+
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|
+ irq_set_handler_data(block->parent_irq, data);
|
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|
|
|
+ irq_set_chained_handler(block->parent_irq,
|
|
|
|
|
+ bcm6345_l2_intc_irq_handle);
|
|
|
|
|
+ bcm6345_periph_irq_handle);
|
|
|
|
|
+ }
|
|
|
|
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+
|
|
|
|
|
+ data->num_words = num_words;
|
|
|
|
|
+
|
|
|
|
|
+ data->chip.name = "bcm6345-l2-intc";
|
|
|
|
|
+ data->chip.irq_mask = bcm6345_l2_intc_irq_mask;
|
|
|
|
|
+ data->chip.irq_unmask = bcm6345_l2_intc_irq_unmask;
|
|
|
|
|
+ data->chip.name = "bcm6345-periph-intc";
|
|
|
|
|
+ data->chip.irq_mask = bcm6345_periph_irq_mask;
|
|
|
|
|
+ data->chip.irq_unmask = bcm6345_periph_irq_unmask;
|
|
|
|
|
+
|
|
|
|
|
+#ifdef CONFIG_SMP
|
|
|
|
|
+ if (num_blocks > 1)
|
|
|
|
|
+ data->chip.set_affinity = bcm6345_l2_intc_set_affinity;
|
|
|
|
|
+ data->chip.irq_set_affinity = bcm6345_periph_set_affinity;
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
|
|
+ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
|
|
|
|
|
+ VIRQ_BASE, &bcm6345_l2_domain_ops,
|
|
|
|
|
+ data);
|
|
|
|
|
+ VIRQ_BASE,
|
|
|
|
|
+ &bcm6345_periph_domain_ops, data);
|
|
|
|
|
+ if (!data->domain) {
|
|
|
|
|
+ kfree(data);
|
|
|
|
|
+ return -EINVAL;
|
|
|
|
|
@ -317,15 +362,15 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
|
|
|
|
+ return 0;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+void __init bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
|
|
|
|
|
+ int num_words)
|
|
|
|
|
+void __init bcm6345_periph_intc_init(int num_blocks, int *irq,
|
|
|
|
|
+ void __iomem **base, int num_words)
|
|
|
|
|
+{
|
|
|
|
|
+ __bcm6345_l2_intc_init(NULL, num_blocks, irq, base, num_words);
|
|
|
|
|
+ __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+#ifdef CONFIG_OF
|
|
|
|
|
+static int __init bcm6345_l2_intc_of_init(struct device_node *node,
|
|
|
|
|
+ struct device_node *parent)
|
|
|
|
|
+static int __init bcm6345_periph_of_init(struct device_node *node,
|
|
|
|
|
+ struct device_node *parent)
|
|
|
|
|
+{
|
|
|
|
|
+ struct resource res;
|
|
|
|
|
+ int num_irqs, ret = -EINVAL;
|
|
|
|
|
@ -374,7 +419,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ ret = __bcm6345_l2_intc_init(node, num_irqs, irqs, bases, words);
|
|
|
|
|
+ ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);
|
|
|
|
|
+ if (!ret)
|
|
|
|
|
+ return 0;
|
|
|
|
|
+
|
|
|
|
|
@ -387,11 +432,11 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
|
|
|
|
+ return ret;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+IRQCHIP_DECLARE(bcm6345_l2_intc, "brcm,bcm6345-l2-intc",
|
|
|
|
|
+ bcm6345_l2_intc_of_init);
|
|
|
|
|
+IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-periph-intc",
|
|
|
|
|
+ bcm6345_periph_of_init);
|
|
|
|
|
+#endif
|
|
|
|
|
--- /dev/null
|
|
|
|
|
+++ b/include/linux/irqchip/irq-bcm6345-l2-intc.h
|
|
|
|
|
+++ b/include/linux/irqchip/irq-bcm6345-periph.h
|
|
|
|
|
@@ -0,0 +1,16 @@
|
|
|
|
|
+/*
|
|
|
|
|
+ * This file is subject to the terms and conditions of the GNU General Public
|
|
|
|
|
@ -402,10 +447,40 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
|
|
|
|
+ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
|
|
|
|
|
+ */
|
|
|
|
|
+
|
|
|
|
|
+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
|
|
|
|
|
+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
|
|
|
|
|
+
|
|
|
|
|
+void bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
|
|
|
|
|
+ int num_words);
|
|
|
|
|
+
|
|
|
|
|
+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H */
|
|
|
|
|
+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
|
|
|
|
|
+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
|
|
|
|
|
+
|
|
|
|
|
+void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,
|
|
|
|
|
+ int num_words);
|
|
|
|
|
+
|
|
|
|
|
+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */
|
|
|
|
|
diff --git a/drivers/irqchip/irq-bcm6345-periph.c b/drivers/irqchip/irq-bcm6345-periph.c
|
|
|
|
|
index dfab88e..b280164 100644
|
|
|
|
|
--- a/drivers/irqchip/irq-bcm6345-periph.c
|
|
|
|
|
+++ b/drivers/irqchip/irq-bcm6345-periph.c
|
|
|
|
|
@@ -149,6 +149,7 @@ static int bcm6345_periph_set_affinity(struct irq_data *data,
|
|
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(data);
|
|
|
|
|
struct intc_data *priv = data->domain->host_data;
|
|
|
|
|
unsigned int i, reg, bit;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
bool enabled;
|
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
|
|
@@ -168,7 +169,7 @@ static int bcm6345_periph_set_affinity(struct irq_data *data,
|
|
|
|
|
if (!priv->block[cpu].parent_irq)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
- raw_spin_lock(&priv->lock);
|
|
|
|
|
+ raw_spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
|
enabled = !irqd_irq_masked(data);
|
|
|
|
|
for (i = 0; i < MAX_PARENT_IRQS; i++) {
|
|
|
|
|
struct intc_block *block = &priv->block[i];
|
|
|
|
|
@@ -184,7 +185,7 @@ static int bcm6345_periph_set_affinity(struct irq_data *data,
|
|
|
|
|
__bcm6345_periph_enable(block, reg, bit, false);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
- raw_spin_unlock(&priv->lock);
|
|
|
|
|
+ raw_spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
Jonas Gorski
10 years ago