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--- a/arch/mips/ath79/common.h
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+++ b/arch/mips/ath79/common.h
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@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask
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void ath79_gpio_function_disable(u32 mask);
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void ath79_gpio_function_setup(u32 set, u32 clear);
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void ath79_gpio_output_select(unsigned gpio, u8 val);
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+int ath79_gpio_direction_select(unsigned gpio, bool oe);
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void ath79_gpio_init(void);
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#endif /* __ATH79_COMMON_H */
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -130,6 +130,30 @@ static int ar934x_gpio_direction_output(
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return 0;
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}
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+int ath79_gpio_direction_select(unsigned gpio, bool oe)
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+{
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long flags;
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+ bool ieq_1 = (soc_is_ar934x() ||
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+ soc_is_qca953x());
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+
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+ if (gpio >= ath79_gpio_count)
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+ return -1;
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+
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+ spin_lock_irqsave(&ath79_gpio_lock, flags);
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+
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+ if ((ieq_1 && oe) || (!ieq_1 && !oe))
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
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+ base + AR71XX_GPIO_REG_OE);
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+ else
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
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+ base + AR71XX_GPIO_REG_OE);
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+
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+
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+ return 0;
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+}
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+
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static struct gpio_chip ath79_gpio_chip = {
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.label = "ath79",
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.get = ath79_gpio_get_value,
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