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96 lines
3.0 KiB
96 lines
3.0 KiB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%define EFLAGS_HAS_CPUID (1<<21)
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%define FLAG_CPUID1_ECX_CLMUL (1<<1)
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%define FLAG_CPUID1_EDX_SSE2 (1<<26)
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%define FLAG_CPUID1_ECX_SSE3 (1)
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%define FLAG_CPUID1_ECX_SSE4_1 (1<<19)
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%define FLAG_CPUID1_ECX_SSE4_2 (1<<20)
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%define FLAG_CPUID1_ECX_POPCNT (1<<23)
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%define FLAG_CPUID1_ECX_AESNI (1<<25)
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%define FLAG_CPUID1_ECX_OSXSAVE (1<<27)
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%define FLAG_CPUID1_ECX_AVX (1<<28)
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%define FLAG_CPUID1_EBX_AVX2 (1<<5)
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%define FLAG_XGETBV_EAX_XMM_YMM 0x6
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%define FLAG_CPUID1_EAX_AVOTON 0x000406d0
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; define d and w variants for registers
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%define raxd eax
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%define raxw ax
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%define raxb al
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%define rbxd ebx
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%define rbxw bx
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%define rbxb bl
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%define rcxd ecx
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%define rcxw cx
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%define rcxb cl
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%define rdxd edx
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%define rdxw dx
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%define rdxb dl
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%define rsid esi
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%define rsiw si
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%define rsib sil
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%define rdid edi
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%define rdiw di
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%define rdib dil
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%define rbpd ebp
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%define rbpw bp
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%define rbpb bpl
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%define ymm0x xmm0
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%define ymm1x xmm1
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%define ymm2x xmm2
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%define ymm3x xmm3
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%define ymm4x xmm4
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%define ymm5x xmm5
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%define ymm6x xmm6
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%define ymm7x xmm7
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%define ymm8x xmm8
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%define ymm9x xmm9
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%define ymm10x xmm10
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%define ymm11x xmm11
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%define ymm12x xmm12
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%define ymm13x xmm13
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%define ymm14x xmm14
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%define ymm15x xmm15
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%define DWORD(reg) reg %+ d
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%define WORD(reg) reg %+ w
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%define BYTE(reg) reg %+ b
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%define XWORD(reg) reg %+ x
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