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48 lines
1.9 KiB
48 lines
1.9 KiB
From 3b2e7c7c83873f4c073d501c2fff80518e264240 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 4 Jan 2016 20:24:00 +0100
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Subject: [PATCH] MIPS: ralink: Add a few missing clocks
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/11995/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/ralink/mt7620.c | 3 +++
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arch/mips/ralink/rt305x.c | 1 +
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arch/mips/ralink/rt3883.c | 1 +
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3 files changed, 5 insertions(+)
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -436,7 +436,10 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000100.timer", periph_rate);
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ralink_clk_add("10000120.watchdog", periph_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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+ ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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+ ralink_clk_add("10000d00.uart1", periph_rate);
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+ ralink_clk_add("10000e00.uart2", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -190,6 +190,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("sys", sys_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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+ ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000100.timer", wdt_rate);
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ralink_clk_add("10000120.watchdog", wdt_rate);
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ralink_clk_add("10000500.uart", uart_rate);
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--- a/arch/mips/ralink/rt3883.c
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+++ b/arch/mips/ralink/rt3883.c
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@@ -99,6 +99,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000120.watchdog", sys_rate);
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ralink_clk_add("10000500.uart", 40000000);
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ralink_clk_add("10000b00.spi", sys_rate);
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+ ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", 40000000);
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ralink_clk_add("10100000.ethernet", sys_rate);
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ralink_clk_add("10180000.wmac", 40000000);
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