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127 lines
3.7 KiB
127 lines
3.7 KiB
From 5c5367d7f9ad835b3b8a2dddfbe90e4c6e669084 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Mon, 12 Aug 2013 14:14:55 -0300
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Subject: [PATCH 122/203] mtd: nand: pxa3xx: Move cached registers to info
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structure
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This registers are not per-chip (aka host) but controller-wide,
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so it's better to store them in the global 'info' structure.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 36 +++++++++++++++++-------------------
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1 file changed, 17 insertions(+), 19 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -144,10 +144,6 @@ struct pxa3xx_nand_host {
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unsigned int row_addr_cycles;
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size_t read_id_bytes;
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- /* cached register value */
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- uint32_t reg_ndcr;
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- uint32_t ndtr0cs0;
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- uint32_t ndtr1cs0;
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};
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struct pxa3xx_nand_info {
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@@ -193,6 +189,11 @@ struct pxa3xx_nand_info {
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unsigned int oob_size;
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int retcode;
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+ /* cached register value */
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+ uint32_t reg_ndcr;
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+ uint32_t ndtr0cs0;
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+ uint32_t ndtr1cs0;
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+
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/* generated NDCBx register values */
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uint32_t ndcb0;
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uint32_t ndcb1;
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@@ -258,8 +259,8 @@ static void pxa3xx_nand_set_timing(struc
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NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
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NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
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- host->ndtr0cs0 = ndtr0;
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- host->ndtr1cs0 = ndtr1;
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+ info->ndtr0cs0 = ndtr0;
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+ info->ndtr1cs0 = ndtr1;
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nand_writel(info, NDTR0CS0, ndtr0);
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nand_writel(info, NDTR1CS0, ndtr1);
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}
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@@ -267,7 +268,7 @@ static void pxa3xx_nand_set_timing(struc
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static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
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{
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struct pxa3xx_nand_host *host = info->host[info->cs];
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- int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
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+ int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
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info->data_size = host->page_size;
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if (!oob_enable) {
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@@ -293,10 +294,9 @@ static void pxa3xx_set_datasize(struct p
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*/
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static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
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{
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- struct pxa3xx_nand_host *host = info->host[info->cs];
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uint32_t ndcr;
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- ndcr = host->reg_ndcr;
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+ ndcr = info->reg_ndcr;
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if (info->use_ecc)
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ndcr |= NDCR_ECC_EN;
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@@ -683,7 +683,7 @@ static void pxa3xx_nand_cmdfunc(struct m
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* "byte" address into a "word" address appropriate
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* for indexing a word-oriented device
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*/
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- if (host->reg_ndcr & NDCR_DWIDTH_M)
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+ if (info->reg_ndcr & NDCR_DWIDTH_M)
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column /= 2;
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/*
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@@ -693,8 +693,8 @@ static void pxa3xx_nand_cmdfunc(struct m
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*/
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if (info->cs != host->cs) {
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info->cs = host->cs;
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- nand_writel(info, NDTR0CS0, host->ndtr0cs0);
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- nand_writel(info, NDTR1CS0, host->ndtr1cs0);
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+ nand_writel(info, NDTR0CS0, info->ndtr0cs0);
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+ nand_writel(info, NDTR1CS0, info->ndtr1cs0);
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}
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info->state = STATE_PREPARED;
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@@ -870,7 +870,7 @@ static int pxa3xx_nand_config_flash(stru
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ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
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ndcr |= NDCR_SPARE_EN; /* enable spare by default */
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- host->reg_ndcr = ndcr;
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+ info->reg_ndcr = ndcr;
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pxa3xx_nand_set_timing(host, f->timing);
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return 0;
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@@ -893,11 +893,9 @@ static int pxa3xx_nand_detect_config(str
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host->read_id_bytes = 2;
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}
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- host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
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-
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- host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
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- host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
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-
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+ info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
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+ info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
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+ info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
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return 0;
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}
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@@ -1044,7 +1042,7 @@ KEEP_CONFIG:
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chip->ecc.size = host->page_size;
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chip->ecc.strength = 1;
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- if (host->reg_ndcr & NDCR_DWIDTH_M)
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+ if (info->reg_ndcr & NDCR_DWIDTH_M)
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chip->options |= NAND_BUSWIDTH_16;
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if (nand_scan_ident(mtd, 1, def))
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