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261 lines
10 KiB
261 lines
10 KiB
From a10349f1710a11239c58da3a7e5b353c6b2070c2 Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:32 +0800
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Subject: [PATCH 153/224] mmc: mediatek: add pad_tune0 support
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from mt2701, the register of PAD_TUNE has been phased out,
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while there is a new register of PAD_TUNE0
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/mtk-sd.c | 51 ++++++++++++++++++++++++++++++-----------------
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1 file changed, 33 insertions(+), 18 deletions(-)
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diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
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index ab2fbbbdfda3..bcd83d6f2b86 100644
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -75,6 +75,7 @@
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#define MSDC_PATCH_BIT 0xb0
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#define MSDC_PATCH_BIT1 0xb4
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#define MSDC_PAD_TUNE 0xec
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+#define MSDC_PAD_TUNE0 0xf0
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#define PAD_DS_TUNE 0x188
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#define PAD_CMD_TUNE 0x18c
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#define EMMC50_CFG0 0x208
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@@ -301,6 +302,7 @@ struct msdc_save_para {
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struct mtk_mmc_compatible {
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u8 clk_div_bits;
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bool hs400_tune; /* only used for MT8173 */
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+ u32 pad_tune_reg;
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};
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struct msdc_tune_para {
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@@ -362,21 +364,25 @@ struct msdc_host {
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static const struct mtk_mmc_compatible mt8135_compat = {
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.clk_div_bits = 8,
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.hs400_tune = false,
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+ .pad_tune_reg = MSDC_PAD_TUNE,
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};
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static const struct mtk_mmc_compatible mt8173_compat = {
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.clk_div_bits = 8,
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.hs400_tune = true,
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+ .pad_tune_reg = MSDC_PAD_TUNE,
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};
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static const struct mtk_mmc_compatible mt2701_compat = {
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.clk_div_bits = 12,
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.hs400_tune = false,
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+ .pad_tune_reg = MSDC_PAD_TUNE0,
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};
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static const struct mtk_mmc_compatible mt2712_compat = {
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.clk_div_bits = 12,
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.hs400_tune = false,
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+ .pad_tune_reg = MSDC_PAD_TUNE0,
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};
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static const struct of_device_id msdc_of_ids[] = {
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@@ -581,6 +587,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
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u32 flags;
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u32 div;
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u32 sclk;
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+ u32 tune_reg = host->dev_comp->pad_tune_reg;
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if (!hz) {
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dev_dbg(host->dev, "set mclk to 0\n");
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@@ -663,10 +670,10 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
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*/
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if (host->sclk <= 52000000) {
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writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
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- writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
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+ writel(host->def_tune_para.pad_tune, host->base + tune_reg);
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} else {
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writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
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- writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
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+ writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
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writel(host->saved_tune_para.pad_cmd_tune,
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host->base + PAD_CMD_TUNE);
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}
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@@ -1224,6 +1231,7 @@ static irqreturn_t msdc_irq(int irq, void *dev_id)
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static void msdc_init_hw(struct msdc_host *host)
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{
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u32 val;
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+ u32 tune_reg = host->dev_comp->pad_tune_reg;
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/* Configure to MMC/SD mode, clock free running */
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sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
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@@ -1239,7 +1247,7 @@ static void msdc_init_hw(struct msdc_host *host)
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val = readl(host->base + MSDC_INT);
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writel(val, host->base + MSDC_INT);
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- writel(0, host->base + MSDC_PAD_TUNE);
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+ writel(0, host->base + tune_reg);
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writel(0, host->base + MSDC_IOCON);
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
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writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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@@ -1259,7 +1267,7 @@ static void msdc_init_hw(struct msdc_host *host)
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sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
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host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
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- host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
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+ host->def_tune_para.pad_tune = readl(host->base + tune_reg);
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dev_dbg(host->dev, "init hardware done!");
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}
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@@ -1402,18 +1410,19 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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struct msdc_delay_phase internal_delay_phase;
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u8 final_delay, final_maxlen;
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u32 internal_delay = 0;
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+ u32 tune_reg = host->dev_comp->pad_tune_reg;
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int cmd_err;
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int i, j;
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if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
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mmc->ios.timing == MMC_TIMING_UHS_SDR104)
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRRDLY,
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host->hs200_cmd_int_delay);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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/*
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* Using the same parameters, it may sometimes pass the test,
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@@ -1437,7 +1446,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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/*
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* Using the same parameters, it may sometimes pass the test,
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@@ -1462,12 +1471,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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final_maxlen = final_fall_delay.maxlen;
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
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+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
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+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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@@ -1475,7 +1484,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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goto skip_internal;
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRRDLY, i);
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mmc_send_tuning(mmc, opcode, &cmd_err);
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if (!cmd_err)
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@@ -1483,7 +1492,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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}
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dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
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internal_delay_phase = get_best_delay(host, internal_delay);
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- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
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+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
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internal_delay_phase.final_phase);
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skip_internal:
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dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
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@@ -1545,12 +1554,13 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
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u8 final_delay, final_maxlen;
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+ u32 tune_reg = host->dev_comp->pad_tune_reg;
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int i, ret;
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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@@ -1565,7 +1575,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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@@ -1578,14 +1588,14 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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- sdr_set_field(host->base + MSDC_PAD_TUNE,
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+ sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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@@ -1599,6 +1609,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct msdc_host *host = mmc_priv(mmc);
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int ret;
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+ u32 tune_reg = host->dev_comp->pad_tune_reg;
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if (host->hs400_mode &&
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host->dev_comp->hs400_tune)
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@@ -1616,7 +1627,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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}
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host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
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- host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
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+ host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
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host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
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return ret;
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}
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@@ -1857,10 +1868,12 @@ static int msdc_drv_remove(struct platform_device *pdev)
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#ifdef CONFIG_PM
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static void msdc_save_reg(struct msdc_host *host)
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{
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+ u32 tune_reg = host->dev_comp->pad_tune_reg;
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+
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host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
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host->save_para.iocon = readl(host->base + MSDC_IOCON);
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host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
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- host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
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+ host->save_para.pad_tune = readl(host->base + tune_reg);
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host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
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host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
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host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
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@@ -1870,10 +1883,12 @@ static void msdc_save_reg(struct msdc_host *host)
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static void msdc_restore_reg(struct msdc_host *host)
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{
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+ u32 tune_reg = host->dev_comp->pad_tune_reg;
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+
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writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
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writel(host->save_para.iocon, host->base + MSDC_IOCON);
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writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
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- writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
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+ writel(host->save_para.pad_tune, host->base + tune_reg);
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writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
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writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
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writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
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--
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2.11.0
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