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242 lines
6.7 KiB
242 lines
6.7 KiB
From 87996dabef0d83bbd2ed5264b83b01224bc42968 Mon Sep 17 00:00:00 2001
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From: Chenglin Xu <chenglin.xu@mediatek.com>
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Date: Wed, 18 Oct 2017 16:28:48 +0800
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Subject: [PATCH 122/224] soc: mediatek: pwrap: add support for MT7622 SoC
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Add the registers, callbacks and data structures required to make the
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PMIC wrapper work on MT7622.
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Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
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Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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drivers/soc/mediatek/mtk-pmic-wrap.c | 170 +++++++++++++++++++++++++++++++++++
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1 file changed, 170 insertions(+)
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diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
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index cbc3f0e82337..5d61d127e1d7 100644
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--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
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+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
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@@ -214,6 +214,36 @@ enum pwrap_regs {
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PWRAP_ADC_RDATA_ADDR1,
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PWRAP_ADC_RDATA_ADDR2,
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+ /* MT7622 only regs */
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+ PWRAP_EINT_STA0_ADR,
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+ PWRAP_EINT_STA1_ADR,
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+ PWRAP_STA,
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+ PWRAP_CLR,
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+ PWRAP_DVFS_ADR8,
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+ PWRAP_DVFS_WDATA8,
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+ PWRAP_DVFS_ADR9,
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+ PWRAP_DVFS_WDATA9,
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+ PWRAP_DVFS_ADR10,
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+ PWRAP_DVFS_WDATA10,
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+ PWRAP_DVFS_ADR11,
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+ PWRAP_DVFS_WDATA11,
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+ PWRAP_DVFS_ADR12,
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+ PWRAP_DVFS_WDATA12,
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+ PWRAP_DVFS_ADR13,
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+ PWRAP_DVFS_WDATA13,
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+ PWRAP_DVFS_ADR14,
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+ PWRAP_DVFS_WDATA14,
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+ PWRAP_DVFS_ADR15,
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+ PWRAP_DVFS_WDATA15,
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+ PWRAP_EXT_CK,
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+ PWRAP_ADC_RDATA_ADDR,
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+ PWRAP_GPS_STA,
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+ PWRAP_SW_RST,
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+ PWRAP_DVFS_STEP_CTRL0,
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+ PWRAP_DVFS_STEP_CTRL1,
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+ PWRAP_DVFS_STEP_CTRL2,
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+ PWRAP_SPI2_CTRL,
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+
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/* MT8135 only regs */
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PWRAP_CSHEXT,
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PWRAP_EVENT_IN_EN,
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@@ -336,6 +366,118 @@ static int mt2701_regs[] = {
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[PWRAP_ADC_RDATA_ADDR2] = 0x154,
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};
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+static int mt7622_regs[] = {
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+ [PWRAP_MUX_SEL] = 0x0,
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+ [PWRAP_WRAP_EN] = 0x4,
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+ [PWRAP_DIO_EN] = 0x8,
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+ [PWRAP_SIDLY] = 0xC,
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+ [PWRAP_RDDMY] = 0x10,
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+ [PWRAP_SI_CK_CON] = 0x14,
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+ [PWRAP_CSHEXT_WRITE] = 0x18,
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+ [PWRAP_CSHEXT_READ] = 0x1C,
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+ [PWRAP_CSLEXT_START] = 0x20,
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+ [PWRAP_CSLEXT_END] = 0x24,
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+ [PWRAP_STAUPD_PRD] = 0x28,
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+ [PWRAP_STAUPD_GRPEN] = 0x2C,
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+ [PWRAP_EINT_STA0_ADR] = 0x30,
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+ [PWRAP_EINT_STA1_ADR] = 0x34,
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+ [PWRAP_STA] = 0x38,
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+ [PWRAP_CLR] = 0x3C,
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+ [PWRAP_STAUPD_MAN_TRIG] = 0x40,
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+ [PWRAP_STAUPD_STA] = 0x44,
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+ [PWRAP_WRAP_STA] = 0x48,
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+ [PWRAP_HARB_INIT] = 0x4C,
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+ [PWRAP_HARB_HPRIO] = 0x50,
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+ [PWRAP_HIPRIO_ARB_EN] = 0x54,
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+ [PWRAP_HARB_STA0] = 0x58,
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+ [PWRAP_HARB_STA1] = 0x5C,
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+ [PWRAP_MAN_EN] = 0x60,
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+ [PWRAP_MAN_CMD] = 0x64,
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+ [PWRAP_MAN_RDATA] = 0x68,
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+ [PWRAP_MAN_VLDCLR] = 0x6C,
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+ [PWRAP_WACS0_EN] = 0x70,
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+ [PWRAP_INIT_DONE0] = 0x74,
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+ [PWRAP_WACS0_CMD] = 0x78,
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+ [PWRAP_WACS0_RDATA] = 0x7C,
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+ [PWRAP_WACS0_VLDCLR] = 0x80,
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+ [PWRAP_WACS1_EN] = 0x84,
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+ [PWRAP_INIT_DONE1] = 0x88,
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+ [PWRAP_WACS1_CMD] = 0x8C,
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+ [PWRAP_WACS1_RDATA] = 0x90,
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+ [PWRAP_WACS1_VLDCLR] = 0x94,
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+ [PWRAP_WACS2_EN] = 0x98,
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+ [PWRAP_INIT_DONE2] = 0x9C,
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+ [PWRAP_WACS2_CMD] = 0xA0,
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+ [PWRAP_WACS2_RDATA] = 0xA4,
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+ [PWRAP_WACS2_VLDCLR] = 0xA8,
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+ [PWRAP_INT_EN] = 0xAC,
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+ [PWRAP_INT_FLG_RAW] = 0xB0,
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+ [PWRAP_INT_FLG] = 0xB4,
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+ [PWRAP_INT_CLR] = 0xB8,
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+ [PWRAP_SIG_ADR] = 0xBC,
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+ [PWRAP_SIG_MODE] = 0xC0,
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+ [PWRAP_SIG_VALUE] = 0xC4,
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+ [PWRAP_SIG_ERRVAL] = 0xC8,
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+ [PWRAP_CRC_EN] = 0xCC,
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+ [PWRAP_TIMER_EN] = 0xD0,
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+ [PWRAP_TIMER_STA] = 0xD4,
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+ [PWRAP_WDT_UNIT] = 0xD8,
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+ [PWRAP_WDT_SRC_EN] = 0xDC,
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+ [PWRAP_WDT_FLG] = 0xE0,
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+ [PWRAP_DEBUG_INT_SEL] = 0xE4,
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+ [PWRAP_DVFS_ADR0] = 0xE8,
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+ [PWRAP_DVFS_WDATA0] = 0xEC,
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+ [PWRAP_DVFS_ADR1] = 0xF0,
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+ [PWRAP_DVFS_WDATA1] = 0xF4,
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+ [PWRAP_DVFS_ADR2] = 0xF8,
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+ [PWRAP_DVFS_WDATA2] = 0xFC,
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+ [PWRAP_DVFS_ADR3] = 0x100,
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+ [PWRAP_DVFS_WDATA3] = 0x104,
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+ [PWRAP_DVFS_ADR4] = 0x108,
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+ [PWRAP_DVFS_WDATA4] = 0x10C,
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+ [PWRAP_DVFS_ADR5] = 0x110,
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+ [PWRAP_DVFS_WDATA5] = 0x114,
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+ [PWRAP_DVFS_ADR6] = 0x118,
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+ [PWRAP_DVFS_WDATA6] = 0x11C,
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+ [PWRAP_DVFS_ADR7] = 0x120,
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+ [PWRAP_DVFS_WDATA7] = 0x124,
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+ [PWRAP_DVFS_ADR8] = 0x128,
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+ [PWRAP_DVFS_WDATA8] = 0x12C,
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+ [PWRAP_DVFS_ADR9] = 0x130,
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+ [PWRAP_DVFS_WDATA9] = 0x134,
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+ [PWRAP_DVFS_ADR10] = 0x138,
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+ [PWRAP_DVFS_WDATA10] = 0x13C,
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+ [PWRAP_DVFS_ADR11] = 0x140,
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+ [PWRAP_DVFS_WDATA11] = 0x144,
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+ [PWRAP_DVFS_ADR12] = 0x148,
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+ [PWRAP_DVFS_WDATA12] = 0x14C,
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+ [PWRAP_DVFS_ADR13] = 0x150,
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+ [PWRAP_DVFS_WDATA13] = 0x154,
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+ [PWRAP_DVFS_ADR14] = 0x158,
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+ [PWRAP_DVFS_WDATA14] = 0x15C,
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+ [PWRAP_DVFS_ADR15] = 0x160,
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+ [PWRAP_DVFS_WDATA15] = 0x164,
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+ [PWRAP_SPMINF_STA] = 0x168,
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+ [PWRAP_CIPHER_KEY_SEL] = 0x16C,
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+ [PWRAP_CIPHER_IV_SEL] = 0x170,
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+ [PWRAP_CIPHER_EN] = 0x174,
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+ [PWRAP_CIPHER_RDY] = 0x178,
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+ [PWRAP_CIPHER_MODE] = 0x17C,
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+ [PWRAP_CIPHER_SWRST] = 0x180,
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+ [PWRAP_DCM_EN] = 0x184,
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+ [PWRAP_DCM_DBC_PRD] = 0x188,
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+ [PWRAP_EXT_CK] = 0x18C,
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+ [PWRAP_ADC_CMD_ADDR] = 0x190,
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+ [PWRAP_PWRAP_ADC_CMD] = 0x194,
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+ [PWRAP_ADC_RDATA_ADDR] = 0x198,
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+ [PWRAP_GPS_STA] = 0x19C,
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+ [PWRAP_SW_RST] = 0x1A0,
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+ [PWRAP_DVFS_STEP_CTRL0] = 0x238,
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+ [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
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+ [PWRAP_DVFS_STEP_CTRL2] = 0x240,
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+ [PWRAP_SPI2_CTRL] = 0x244,
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+};
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+
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static int mt8173_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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@@ -499,6 +641,7 @@ enum pmic_type {
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enum pwrap_type {
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PWRAP_MT2701,
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+ PWRAP_MT7622,
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PWRAP_MT8135,
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PWRAP_MT8173,
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};
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@@ -927,6 +1070,9 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
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case PWRAP_MT8173:
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pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
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break;
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+ case PWRAP_MT7622:
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+ pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
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+ break;
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}
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/* Config cipher mode @PMIC */
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@@ -1071,6 +1217,15 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
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return 0;
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}
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+static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
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+{
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+ pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
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+ /* enable 2wire SPI master */
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+ pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
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+
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+ return 0;
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+}
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+
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static int pwrap_init(struct pmic_wrapper *wrp)
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{
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int ret;
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@@ -1242,6 +1397,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
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.init_soc_specific = pwrap_mt2701_init_soc_specific,
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};
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+static const struct pmic_wrapper_type pwrap_mt7622 = {
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+ .regs = mt7622_regs,
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+ .type = PWRAP_MT7622,
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+ .arb_en_all = 0xff,
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+ .int_en_all = ~(u32)BIT(31),
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+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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+ .has_bridge = 0,
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+ .init_reg_clock = pwrap_common_init_reg_clock,
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+ .init_soc_specific = pwrap_mt7622_init_soc_specific,
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+};
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+
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static const struct pmic_wrapper_type pwrap_mt8135 = {
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.regs = mt8135_regs,
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.type = PWRAP_MT8135,
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@@ -1271,6 +1438,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
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.compatible = "mediatek,mt2701-pwrap",
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.data = &pwrap_mt2701,
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}, {
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+ .compatible = "mediatek,mt7622-pwrap",
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+ .data = &pwrap_mt7622,
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+ }, {
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.compatible = "mediatek,mt8135-pwrap",
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.data = &pwrap_mt8135,
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}, {
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--
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2.11.0
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