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105 lines
3.2 KiB
105 lines
3.2 KiB
From a8e8c90a3cc81c6a7a44ff7fb18ceb71978c9155 Mon Sep 17 00:00:00 2001
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From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
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Date: Thu, 13 Feb 2014 18:21:23 +0200
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Subject: [PATCH 066/182] spi: qup: Add device tree bindings information
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The Qualcomm Universal Peripheral (QUP) core is an
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AHB slave that provides a common data path (an output
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FIFO and an input FIFO) for serial peripheral interface
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(SPI) mini-core.
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Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
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Signed-off-by: Mark Brown <broonie@linaro.org>
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---
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.../devicetree/bindings/spi/qcom,spi-qup.txt | 85 ++++++++++++++++++++
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1 file changed, 85 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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@@ -0,0 +1,85 @@
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+Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
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+
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+The QUP core is an AHB slave that provides a common data path (an output FIFO
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+and an input FIFO) for serial peripheral interface (SPI) mini-core.
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+
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+SPI in master mode supports up to 50MHz, up to four chip selects, programmable
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+data path from 4 bits to 32 bits and numerous protocol variants.
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+
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+Required properties:
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+- compatible: Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
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+- reg: Should contain base register location and length
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+- interrupts: Interrupt number used by this controller
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+
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+- clocks: Should contain the core clock and the AHB clock.
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+- clock-names: Should be "core" for the core clock and "iface" for the
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+ AHB clock.
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+
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+- #address-cells: Number of cells required to define a chip select
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+ address on the SPI bus. Should be set to 1.
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+- #size-cells: Should be zero.
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+
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+Optional properties:
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+- spi-max-frequency: Specifies maximum SPI clock frequency,
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+ Units - Hz. Definition as per
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+ Documentation/devicetree/bindings/spi/spi-bus.txt
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+
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+SPI slave nodes must be children of the SPI master node and can contain
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+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
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+
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+Example:
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+
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+ spi_8: spi@f9964000 { /* BLSP2 QUP2 */
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+
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+ compatible = "qcom,spi-qup-v2";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0xf9964000 0x1000>;
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+ interrupts = <0 102 0>;
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+ spi-max-frequency = <19200000>;
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+
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+ clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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+ clock-names = "core", "iface";
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi8_default>;
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+
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+ device@0 {
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+ compatible = "arm,pl022-dummy";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ reg = <0>; /* Chip select 0 */
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+ spi-max-frequency = <19200000>;
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+ spi-cpol;
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+ };
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+
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+ device@1 {
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+ compatible = "arm,pl022-dummy";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ reg = <1>; /* Chip select 1 */
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+ spi-max-frequency = <9600000>;
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+ spi-cpha;
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+ };
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+
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+ device@2 {
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+ compatible = "arm,pl022-dummy";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ reg = <2>; /* Chip select 2 */
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+ spi-max-frequency = <19200000>;
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+ spi-cpol;
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+ spi-cpha;
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+ };
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+
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+ device@3 {
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+ compatible = "arm,pl022-dummy";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ reg = <3>; /* Chip select 3 */
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+ spi-max-frequency = <19200000>;
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+ spi-cpol;
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+ spi-cpha;
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+ spi-cs-high;
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+ };
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+ };
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