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174 lines
4.4 KiB
174 lines
4.4 KiB
From 8e843640b3c4a43b963332fdc7b233948ad25a5b Mon Sep 17 00:00:00 2001
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From: Rohit Vaswani <rvaswani@codeaurora.org>
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Date: Tue, 21 May 2013 19:13:50 -0700
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Subject: [PATCH 013/182] ARM: qcom: Add SMP support for KPSSv1
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Implement support for the Krait CPU release sequence when the
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CPUs are part of the first version of the krait processor
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subsystem.
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Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/mach-qcom/platsmp.c | 106 +++++++++++++++++++++++++++++++++++++++++
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arch/arm/mach-qcom/scm-boot.h | 8 ++--
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2 files changed, 111 insertions(+), 3 deletions(-)
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--- a/arch/arm/mach-qcom/platsmp.c
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+++ b/arch/arm/mach-qcom/platsmp.c
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@@ -26,6 +26,16 @@
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#define SCSS_CPU1CORE_RESET 0x2d80
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#define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64
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+#define APCS_CPU_PWR_CTL 0x04
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+#define PLL_CLAMP BIT(8)
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+#define CORE_PWRD_UP BIT(7)
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+#define COREPOR_RST BIT(5)
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+#define CORE_RST BIT(4)
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+#define L2DT_SLP BIT(3)
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+#define CLAMP BIT(0)
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+
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+#define APCS_SAW2_VCTL 0x14
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+
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extern void secondary_startup(void);
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static DEFINE_SPINLOCK(boot_lock);
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@@ -71,6 +81,85 @@ static int scss_release_secondary(unsign
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return 0;
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}
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+static int kpssv1_release_secondary(unsigned int cpu)
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+{
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+ int ret = 0;
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+ void __iomem *reg, *saw_reg;
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+ struct device_node *cpu_node, *acc_node, *saw_node;
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+ u32 val;
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+
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+ cpu_node = of_get_cpu_node(cpu, NULL);
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+ if (!cpu_node)
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+ return -ENODEV;
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+
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+ acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
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+ if (!acc_node) {
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+ ret = -ENODEV;
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+ goto out_acc;
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+ }
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+
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+ saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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+ if (!saw_node) {
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+ ret = -ENODEV;
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+ goto out_saw;
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+ }
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+
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+ reg = of_iomap(acc_node, 0);
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+ if (!reg) {
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+ ret = -ENOMEM;
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+ goto out_acc_map;
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+ }
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+
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+ saw_reg = of_iomap(saw_node, 0);
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+ if (!saw_reg) {
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+ ret = -ENOMEM;
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+ goto out_saw_map;
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+ }
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+
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+ /* Turn on CPU rail */
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+ writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
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+ mb();
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+ udelay(512);
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+
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+ /* Krait bring-up sequence */
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+ val = PLL_CLAMP | L2DT_SLP | CLAMP;
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+ writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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+ val &= ~L2DT_SLP;
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+ writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+ ndelay(300);
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+
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+ val |= COREPOR_RST;
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+ writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+ udelay(2);
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+
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+ val &= ~CLAMP;
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+ writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+ udelay(2);
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+
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+ val &= ~COREPOR_RST;
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+ writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+ udelay(100);
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+
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+ val |= CORE_PWRD_UP;
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+ writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
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+ mb();
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+
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+ iounmap(saw_reg);
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+out_saw_map:
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+ iounmap(reg);
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+out_acc_map:
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+ of_node_put(saw_node);
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+out_saw:
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+ of_node_put(acc_node);
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+out_acc:
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+ of_node_put(cpu_node);
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+ return ret;
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+}
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+
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static DEFINE_PER_CPU(int, cold_boot_done);
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static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
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@@ -110,6 +199,11 @@ static int msm8660_boot_secondary(unsign
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return qcom_boot_secondary(cpu, scss_release_secondary);
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}
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+static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
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+{
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+ return qcom_boot_secondary(cpu, kpssv1_release_secondary);
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+}
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+
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static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu, map;
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@@ -117,6 +211,8 @@ static void __init qcom_smp_prepare_cpus
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static const int cold_boot_flags[] = {
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0,
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SCM_FLAG_COLDBOOT_CPU1,
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+ SCM_FLAG_COLDBOOT_CPU2,
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+ SCM_FLAG_COLDBOOT_CPU3,
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};
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for_each_present_cpu(cpu) {
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@@ -147,3 +243,13 @@ static struct smp_operations smp_msm8660
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#endif
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};
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CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
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+
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+static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
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+ .smp_prepare_cpus = qcom_smp_prepare_cpus,
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+ .smp_secondary_init = qcom_secondary_init,
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+ .smp_boot_secondary = kpssv1_boot_secondary,
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+#ifdef CONFIG_HOTPLUG_CPU
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+ .cpu_die = qcom_cpu_die,
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+#endif
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+};
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+CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
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--- a/arch/arm/mach-qcom/scm-boot.h
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+++ b/arch/arm/mach-qcom/scm-boot.h
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@@ -13,9 +13,11 @@
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#define __MACH_SCM_BOOT_H
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#define SCM_BOOT_ADDR 0x1
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-#define SCM_FLAG_COLDBOOT_CPU1 0x1
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-#define SCM_FLAG_WARMBOOT_CPU1 0x2
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-#define SCM_FLAG_WARMBOOT_CPU0 0x4
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+#define SCM_FLAG_COLDBOOT_CPU1 0x01
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+#define SCM_FLAG_COLDBOOT_CPU2 0x08
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+#define SCM_FLAG_COLDBOOT_CPU3 0x20
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+#define SCM_FLAG_WARMBOOT_CPU0 0x04
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+#define SCM_FLAG_WARMBOOT_CPU1 0x02
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int scm_set_boot_addr(phys_addr_t addr, int flags);
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