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474 lines
13 KiB
474 lines
13 KiB
This driver implements the hw_pci operations needed by the core ARM
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PCI code to setup PCI devices and get their corresponding IRQs, and
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the pci_ops operations that are used by the PCI core to read/write the
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configuration space of PCI devices.
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In addition, this driver enumerates the different PCIe slots, and for
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those having a device plugged in, it allocates the necessary address
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decoding windows, using the new armada_370_xp_alloc_pcie_window()
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function from mach-mvebu/addr-map.c.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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.../devicetree/bindings/pci/armada-370-xp-pcie.txt | 136 +++++++++
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arch/arm/mach-mvebu/Makefile | 1 +
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arch/arm/mach-mvebu/pcie.c | 306 ++++++++++++++++++++
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3 files changed, 443 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pci/armada-370-xp-pcie.txt
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create mode 100644 arch/arm/mach-mvebu/pcie.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/armada-370-xp-pcie.txt
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@@ -0,0 +1,136 @@
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+* Marvell Armada 370/XP PCIe interfaces
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+
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+Mandatory properties:
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+- compatible: must be "marvell,armada-370-xp-pcie"
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+- status: either "disabled" or "okay"
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+- #address-cells, set to <1>
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+- #size-cells, set to <1>
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+- ranges: describes the association between the physical addresses of
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+ the PCIe registers for each PCIe interface with "virtual" addresses
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+ as seen by the sub-nodes. One entry per PCIe interface. Each entry
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+ must have 3 values: the "virtual" address seen by the sub-nodes, the
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+ real physical address of the PCIe registers, and the size.
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+
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+In addition, the Device Tree node must have sub-nodes describing each
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+PCIe interface, having the following mandatory properties:
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+- reg: the address and size of the PCIe registers (translated
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+ addresses according to the ranges property of the parent)
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+- interrupts: the interrupt number of this PCIe interface
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+- clocks: the clock associated to this PCIe interface
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+- marvell,pcie-port: the physical PCIe port number
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+- status: either "disabled" or "okay"
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+
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+and the following optional properties:
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+- marvell,pcie-lane: the physical PCIe lane number, for ports having
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+ multiple lanes. If this property is not found, we assume that the
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+ value is 0.
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+
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+Example:
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+
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+pcie-controller {
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+ compatible = "marvell,armada-370-xp-pcie";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
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+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
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+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
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+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
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+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
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+ 0x10000 0xd0080000 0x2000 /* port1x1_port0 */
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+ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */
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+ 0x14000 0xd0084000 0x2000 /* port1x1_port1 */
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+ 0x18000 0xd0088000 0x2000 /* port1x1_port2 */
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+ 0x1C000 0xd008C000 0x2000 /* port1x1_port3 */>;
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+
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+ pcie0.0@0xd0040000 {
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+ reg = <0x0 0x2000>;
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+ interrupts = <58>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.1@0xd0044000 {
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+ reg = <0x4000 0x2000>;
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+ interrupts = <59>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <1>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.2@0xd0048000 {
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+ reg = <0x8000 0x2000>;
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+ interrupts = <60>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <2>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.3@0xd004C000 {
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+ reg = <0xC000 0x2000>;
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+ interrupts = <61>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <3>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.0@0xd0040000 {
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+ reg = <0x10000 0x2000>;
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+ interrupts = <62>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.1@0xd0044000 {
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+ reg = <0x14000 0x2000>;
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+ interrupts = <63>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <1>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.2@0xd0048000 {
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+ reg = <0x18000 0x2000>;
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+ interrupts = <64>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <2>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.3@0xd004C000 {
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+ reg = <0x1C000 0x2000>;
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+ interrupts = <65>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <3>;
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+ status = "disabled";
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+ };
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+
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+ pcie2@0xd0042000 {
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+ reg = <0x2000 0x2000>;
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+ interrupts = <99>;
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+ clocks = <&gateclk 7>;
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+ marvell,pcie-port = <2>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie3@0xd0082000 {
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+ reg = <0x12000 0x2000>;
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+ interrupts = <103>;
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+ clocks = <&gateclk 8>;
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+ marvell,pcie-port = <3>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+};
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+
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--- a/arch/arm/mach-mvebu/Makefile
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+++ b/arch/arm/mach-mvebu/Makefile
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@@ -7,3 +7,4 @@ obj-y += system-controller.o
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obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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+obj-$(CONFIG_PCI) += pcie.o
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--- /dev/null
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+++ b/arch/arm/mach-mvebu/pcie.c
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@@ -0,0 +1,306 @@
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+/*
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+ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/pci.h>
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+#include <linux/clk.h>
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+#include <linux/module.h>
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+#include <linux/slab.h>
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+#include <linux/platform_device.h>
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+#include <linux/of_address.h>
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+#include <linux/of_pci.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_platform.h>
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+#include <plat/pcie.h>
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+#include "common.h"
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+
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+struct pcie_port {
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+ u8 root_bus_nr;
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+ void __iomem *base;
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+ spinlock_t conf_lock;
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+ int irq;
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+ struct resource res;
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+ int haslink;
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+ u32 port;
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+ u32 lane;
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+ struct clk *clk;
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+};
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+
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+static struct pcie_port *pcie_ports;
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+
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+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
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+{
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+ /*
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+ * Don't go out when trying to access --
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+ * 1. nonexisting device on local bus
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+ * 2. where there's no device connected (no link)
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+ */
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+ if (bus == pp->root_bus_nr && dev == 0)
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+ return 1;
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+
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+ if (!orion_pcie_link_up(pp->base))
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+ return 0;
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+
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+ if (bus == pp->root_bus_nr && dev != 1)
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+ return 0;
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+
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+ return 1;
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+}
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+
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+/*
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+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
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+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
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+ * transactions are atomic.
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+ */
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+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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+ int size, u32 *val)
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+{
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+ struct pci_sys_data *sys = bus->sysdata;
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+ struct pcie_port *pp = sys->private_data;
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+ unsigned long flags;
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+ int ret;
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+
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+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
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+ *val = 0xffffffff;
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ }
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+
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+ spin_lock_irqsave(&pp->conf_lock, flags);
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+ ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
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+ spin_unlock_irqrestore(&pp->conf_lock, flags);
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+
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+ return ret;
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+}
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+
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+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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+ int where, int size, u32 val)
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+{
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+ struct pci_sys_data *sys = bus->sysdata;
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+ struct pcie_port *pp = sys->private_data;
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+ unsigned long flags;
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+ int ret;
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+
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+ if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ spin_lock_irqsave(&pp->conf_lock, flags);
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+ ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
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+ spin_unlock_irqrestore(&pp->conf_lock, flags);
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+
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+ return ret;
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+}
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+
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+static struct pci_ops pcie_ops = {
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+ .read = pcie_rd_conf,
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+ .write = pcie_wr_conf,
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+};
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+
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+/*
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+ * Returns 0 when the device could not be initialized, 1 when
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+ * initialization is successful
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+ */
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+static int __init armada_370_xp_pcie_setup(int nr, struct pci_sys_data *sys)
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+{
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+ struct pcie_port *port = &pcie_ports[nr];
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+ unsigned long membase, iobase;
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+ int ret;
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+
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+ if (!port->haslink)
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+ return 0;
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+
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+ sys->private_data = port;
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+ port->root_bus_nr = sys->busnr;
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+ spin_lock_init(&port->conf_lock);
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+
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+ ret = armada_370_xp_alloc_pcie_window(port->port, port->lane,
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+ IORESOURCE_MEM, SZ_64M, &membase);
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+ if (ret) {
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+ pr_err("PCIe%d.%d: Cannot get memory window, device disabled\n",
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+ port->port, port->lane);
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+ return 0;
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+ }
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+
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+ ret = armada_370_xp_alloc_pcie_window(port->port, port->lane,
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+ IORESOURCE_IO, SZ_64K, &iobase);
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+ if (ret) {
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+ pr_err("PCIe%d.%d: Cannot get I/O window, device disabled\n",
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+ port->port, port->lane);
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+ armada_370_xp_free_pcie_window(IORESOURCE_MEM, membase, SZ_64M);
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+ return 0;
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+ }
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+
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+ port->res.name = kasprintf(GFP_KERNEL, "PCIe %d.%d MEM",
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+ port->port, port->lane);
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+ if (!port->res.name) {
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+ armada_370_xp_free_pcie_window(IORESOURCE_IO, iobase, SZ_64K);
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+ armada_370_xp_free_pcie_window(IORESOURCE_MEM, membase, SZ_64M);
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+ return 0;
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+ }
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+
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+ port->res.start = membase;
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+ port->res.end = membase + SZ_32M - 1;
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+ port->res.flags = IORESOURCE_MEM;
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+
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+ pci_ioremap_io(SZ_64K * sys->busnr, iobase);
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+
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+ if (request_resource(&iomem_resource, &port->res)) {
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+ pr_err("PCIe%d.%d: Cannot request memory resource\n",
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+ port->port, port->lane);
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+ kfree(port->res.name);
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+ armada_370_xp_free_pcie_window(IORESOURCE_IO, iobase, SZ_64K);
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+ armada_370_xp_free_pcie_window(IORESOURCE_MEM, membase, SZ_64M);
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+ return 0;
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+ }
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+
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+ pci_add_resource_offset(&sys->resources, &port->res, sys->mem_offset);
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+
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+ orion_pcie_set_local_bus_nr(port->base, sys->busnr);
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+ orion_pcie_setup(port->base);
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+
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+ return 1;
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+}
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+
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+static void rc_pci_fixup(struct pci_dev *dev)
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+{
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+ /*
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+ * Prevent enumeration of root complex.
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+ */
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+ if (dev->bus->parent == NULL && dev->devfn == 0) {
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+ int i;
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+
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+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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+ dev->resource[i].start = 0;
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+ dev->resource[i].end = 0;
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+ dev->resource[i].flags = 0;
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+ }
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+ }
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+}
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
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+
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+static int __init armada_370_xp_pcie_map_irq(const struct pci_dev *dev, u8 slot,
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+ u8 pin)
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+{
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+ struct pci_sys_data *sys = dev->sysdata;
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+ struct pcie_port *port = sys->private_data;
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+
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+ return port->irq;
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+}
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+
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+static struct hw_pci armada_370_xp_pci __initdata = {
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+ .setup = armada_370_xp_pcie_setup,
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+ .map_irq = armada_370_xp_pcie_map_irq,
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+ .ops = &pcie_ops,
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+};
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+
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+static int __init armada_370_xp_pcie_probe(struct platform_device *pdev)
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+{
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+ struct device_node *child;
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+ int nports, i;
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+
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+ nports = 0;
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+ for_each_child_of_node(pdev->dev.of_node, child) {
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+ if (!of_device_is_available(child))
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+ continue;
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+ nports++;
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+ }
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+
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+ pcie_ports = devm_kzalloc(&pdev->dev, nports * sizeof(*pcie_ports),
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+ GFP_KERNEL);
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+ if (!pcie_ports)
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+ return -ENOMEM;
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+
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+ i = 0;
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+ for_each_child_of_node(pdev->dev.of_node, child) {
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+ struct pcie_port *port = &pcie_ports[i];
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+
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+ if (!of_device_is_available(child))
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+ continue;
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+
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+ if (of_property_read_u32(child, "marvell,pcie-port",
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+ &port->port))
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+ continue;
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+
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+ if (of_property_read_u32(child, "marvell,pcie-lane",
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+ &port->lane))
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+ port->lane = 0;
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+
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+ port->base = of_iomap(child, 0);
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+ if (!port->base) {
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+ dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
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+ port->port, port->lane);
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+ continue;
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+ }
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+
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+ if (orion_pcie_link_up(port->base)) {
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+ port->haslink = 1;
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+ dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
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+ port->port, port->lane);
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+ } else {
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+ port->haslink = 0;
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+ dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
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+ port->port, port->lane);
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+ iounmap(port->base);
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+ continue;
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+ }
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+
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+ port->irq = irq_of_parse_and_map(child, 0);
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+ if (port->irq == 0) {
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+ dev_err(&pdev->dev, "PCIe%d.%d: cannot parse and map IRQ\n",
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+ port->port, port->lane);
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+ iounmap(port->base);
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+ port->haslink = 0;
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+ continue;
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+ }
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+
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+ port->clk = of_clk_get_by_name(child, NULL);
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+ if (!port->clk) {
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+ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
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+ port->port, port->lane);
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+ irq_dispose_mapping(port->irq);
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+ iounmap(port->base);
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+ port->haslink = 0;
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+ continue;
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+ }
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+
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+ clk_prepare_enable(port->clk);
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+
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+ i++;
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+ }
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+
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+ armada_370_xp_pci.nr_controllers = nports;
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+ pci_common_init(&armada_370_xp_pci);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id armada_370_xp_pcie_of_match_table[] = {
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+ { .compatible = "marvell,armada-370-xp-pcie", },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, armada_370_xp_pcie_of_match_table);
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+
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+static struct platform_driver armada_370_xp_pcie_driver = {
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+ .driver = {
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+ .owner = THIS_MODULE,
|
|
+ .name = "armada-370-xp-pcie",
|
|
+ .of_match_table =
|
|
+ of_match_ptr(armada_370_xp_pcie_of_match_table),
|
|
+ },
|
|
+};
|
|
+
|
|
+static int armada_370_xp_pcie_init(void)
|
|
+{
|
|
+ return platform_driver_probe(&armada_370_xp_pcie_driver,
|
|
+ armada_370_xp_pcie_probe);
|
|
+}
|
|
+
|
|
+subsys_initcall(armada_370_xp_pcie_init);
|
|
+
|
|
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
|
|
+MODULE_DESCRIPTION("Marvell Armada 370/XP PCIe driver");
|
|
+MODULE_LICENSE("GPL");
|
|
|