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295 lines
8.9 KiB
295 lines
8.9 KiB
From 121ec6539abedbc0e975cf35f48ee044b323e4c3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Tue, 16 Jun 2015 17:14:26 +0200
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Subject: [PATCH v3 5/6] usb: bcma: add USB 3.0 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/usb/host/bcma-hcd.c | 225 ++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 225 insertions(+)
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--- a/drivers/usb/host/bcma-hcd.c
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+++ b/drivers/usb/host/bcma-hcd.c
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@@ -28,6 +28,7 @@
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#include <linux/of_gpio.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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+#include <linux/usb/xhci_pdriver.h>
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MODULE_AUTHOR("Hauke Mehrtens");
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MODULE_DESCRIPTION("Common USB driver for BCMA Bus");
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@@ -37,6 +38,7 @@ struct bcma_hcd_device {
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struct bcma_device *core;
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struct platform_device *ehci_dev;
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struct platform_device *ohci_dev;
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+ struct platform_device *xhci_dev;
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};
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/* Wait for bitmask in a register to get set or cleared.
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@@ -250,6 +252,10 @@ static const struct usb_ehci_pdata ehci_
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static const struct usb_ohci_pdata ohci_pdata = {
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};
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+static const struct usb_xhci_pdata xhci_pdata = {
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+ .usb3_fake_doorbell = 1
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+};
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+
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static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev,
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const char *name, u32 addr,
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const void *data,
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@@ -343,6 +349,216 @@ err_unregister_ohci_dev:
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return err;
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}
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+static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
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+ u32 value, int timeout)
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+{
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+ unsigned long deadline = jiffies + timeout;
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+ u32 val;
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+
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+ do {
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+ val = readl(addr);
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+ if ((val & mask) == value)
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+ return true;
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+ cpu_relax();
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+ udelay(10);
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+ } while (!time_after_eq(jiffies, deadline));
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+
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+ pr_err("Timeout waiting for register %p\n", addr);
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+
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+ return false;
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+}
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+
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+static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd)
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+{
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+ struct bcma_device *core = bcma_hcd->core;
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+ struct bcma_bus *bus = core->bus;
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+ struct bcma_chipinfo *chipinfo = &bus->chipinfo;
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+ struct bcma_drv_cc_b *ccb = &bus->drv_cc_b;
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+ struct bcma_device *arm_core;
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+ void __iomem *dmu = NULL;
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+ u32 cru_straps_ctrl;
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+
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+ if (chipinfo->id != BCMA_CHIP_ID_BCM4707 &&
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+ chipinfo->id != BCMA_CHIP_ID_BCM53018)
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+ return;
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+
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+ arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9);
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+ if (!arm_core)
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+ return;
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+
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+ dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000);
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+ if (!dmu)
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+ goto out;
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+
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+ /* Check strapping of PCIE/USB3 SEL */
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+ cru_straps_ctrl = ioread32(dmu + 0x2a0);
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+ if ((cru_straps_ctrl & 0x10) == 0)
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+ goto out;
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+
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+ /* Perform USB3 system soft reset */
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+ bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
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+
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+ /* Enable MDIO. Setting MDCDIV as 26 */
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+ iowrite32(0x0000009a, ccb->mii + 0x000);
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+ udelay(2);
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+
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+ switch (chipinfo->id) {
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+ case BCMA_CHIP_ID_BCM4707:
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+ if (chipinfo->rev == 4) {
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+ /* For NS-B0, USB3 PLL Block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8000, ccb->mii + 0x004);
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+
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+ /* Clear ana_pllSeqStart */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58061000, ccb->mii + 0x004);
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+
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+ /* CMOS Divider ratio to 25 */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582a6400, ccb->mii + 0x004);
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+
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+ /* Asserting PLL Reset */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582ec000, ccb->mii + 0x004);
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+
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+ /* Deaaserting PLL Reset */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582e8000, ccb->mii + 0x004);
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+
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+ /* Deasserting USB3 system reset */
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+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+
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+ /* Set ana_pllSeqStart */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58069000, ccb->mii + 0x004);
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+
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+ /* RXPMD block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8020, ccb->mii + 0x004);
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+
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+ /* CDR int loop locking BW to 1 */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58120049, ccb->mii + 0x004);
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+
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+ /* CDR int loop acquisition BW to 1 */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580e0049, ccb->mii + 0x004);
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+
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+ /* CDR prop loop BW to 1 */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580a005c, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ } else {
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+ /* PLL30 block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8000, ccb->mii + 0x004);
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+
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582a6400, ccb->mii + 0x004);
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+
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e80e0, ccb->mii + 0x004);
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+
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580a009c, ccb->mii + 0x004);
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+
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+ /* Enable SSC */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8040, ccb->mii + 0x004);
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+
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580a21d3, ccb->mii + 0x004);
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+
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58061003, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+
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+ /* Deasserting USB3 system reset */
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+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+ }
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+ break;
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+ case BCMA_CHIP_ID_BCM53018:
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+ /* USB3 PLL Block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8000, ccb->mii + 0x004);
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+
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+ /* Assert Ana_Pllseq start */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58061000, ccb->mii + 0x004);
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+
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+ /* Assert CML Divider ratio to 26 */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582a6400, ccb->mii + 0x004);
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+
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+ /* Asserting PLL Reset */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582ec000, ccb->mii + 0x004);
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+
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+ /* Deaaserting PLL Reset */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x582e8000, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+
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+ /* Deasserting USB3 system reset */
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+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
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+
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+ /* PLL frequency monitor enable */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58069000, ccb->mii + 0x004);
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+
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+ /* PIPE Block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8060, ccb->mii + 0x004);
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+
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+ /* CMPMAX & CMPMINTH setting */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580af30d, ccb->mii + 0x004);
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+
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+ /* DEGLITCH MIN & MAX setting */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x580e6302, ccb->mii + 0x004);
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+
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+ /* TXPMD block */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x587e8040, ccb->mii + 0x004);
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+
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+ /* Enabling SSC */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+ iowrite32(0x58061003, ccb->mii + 0x004);
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+
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+ /* Waiting MII Mgt interface idle */
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+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000);
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+
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+ break;
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+ }
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+out:
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+ if (dmu)
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+ iounmap(dmu);
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+}
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+
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+static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd)
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+{
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+ struct bcma_device *core = bcma_hcd->core;
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+
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+ bcma_core_enable(core, 0);
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+
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+ bcma_hcd_usb30_phy_init(bcma_hcd);
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+
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+ bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr,
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+ &xhci_pdata,
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+ sizeof(xhci_pdata));
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+ if (IS_ERR(bcma_hcd->ohci_dev))
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+ return PTR_ERR(bcma_hcd->ohci_dev);
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+
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+ return 0;
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+}
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+
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static int bcma_hcd_probe(struct bcma_device *dev)
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{
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int err;
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@@ -365,6 +581,11 @@ static int bcma_hcd_probe(struct bcma_de
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if (err)
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return err;
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break;
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+ case BCMA_CORE_NS_USB30:
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+ err = bcma_hcd_usb30_init(usb_dev);
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+ if (err)
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+ return err;
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+ break;
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default:
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return -ENODEV;
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}
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@@ -378,11 +599,14 @@ static void bcma_hcd_remove(struct bcma_
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struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
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struct platform_device *ohci_dev = usb_dev->ohci_dev;
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struct platform_device *ehci_dev = usb_dev->ehci_dev;
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+ struct platform_device *xhci_dev = usb_dev->xhci_dev;
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if (ohci_dev)
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platform_device_unregister(ohci_dev);
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if (ehci_dev)
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platform_device_unregister(ehci_dev);
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+ if (xhci_dev)
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+ platform_device_unregister(xhci_dev);
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bcma_core_disable(dev, 0);
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}
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@@ -419,6 +643,7 @@ static int bcma_hcd_resume(struct bcma_d
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static const struct bcma_device_id bcma_hcd_table[] = {
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BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS),
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BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS),
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+ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS),
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{},
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};
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MODULE_DEVICE_TABLE(bcma, bcma_hcd_table);
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