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143 lines
2.3 KiB
143 lines
2.3 KiB
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include "mt7628an.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "cudy,wr1000", "mediatek,mt7628an-soc";
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model = "Cudy WR1000";
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aliases {
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led-boot = &led_wps;
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led-failsafe = &led_wps;
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led-upgrade = &led_wps;
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "rfkill";
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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lan1 {
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label = "wr1000:blue:lan1";
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gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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};
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lan2 {
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label = "wr1000:blue:lan2";
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gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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};
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wan {
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label = "wr1000:blue:wan";
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gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
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};
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wlan2g {
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label = "wr1000:blue:wlan2g";
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gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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led_wps: wps {
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label = "wr1000:blue:wps";
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gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "i2s", "refclk", "wdt", "p4led_an",
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"p3led_an", "p2led_an", "wled_an";
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ralink,function = "gpio";
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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led {
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led-sources = <2>;
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led-active-low;
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};
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};
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};
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&wmac {
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status = "okay";
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};
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ðernet {
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mtd-mac-address = <&factory 0x2e>;
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mediatek,portmap = "llllw";
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};
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