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214 lines
6.2 KiB
214 lines
6.2 KiB
From edd237c93d564e698e169a89d1b1b35248c5ef4a Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 3 Dec 2012 21:44:30 +0100
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Subject: [PATCH 105/123] MIPS: lantiq: rework external irq code
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This code makes the irqs used by the EIU loadable from the DT. Additionally we
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add a helper that allows the pinctrl layer to map external irqs to real irq
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numbers.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/mach-lantiq/lantiq.h | 1 +
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arch/mips/lantiq/irq.c | 104 +++++++++++++++++++---------
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2 files changed, 73 insertions(+), 32 deletions(-)
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diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
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index 76be7a0..f196cce 100644
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--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
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@@ -34,6 +34,7 @@ extern spinlock_t ebu_lock;
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extern void ltq_disable_irq(struct irq_data *data);
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extern void ltq_mask_and_ack_irq(struct irq_data *data);
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extern void ltq_enable_irq(struct irq_data *data);
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+extern int ltq_eiu_get_irq(int exin);
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/* clock handling */
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extern int clk_activate(struct clk *clk);
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diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
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index f36acd1..48407f6 100644
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--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -33,17 +33,10 @@
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/* register definitions - external irqs */
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#define LTQ_EIU_EXIN_C 0x0000
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#define LTQ_EIU_EXIN_INIC 0x0004
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+#define LTQ_EIU_EXIN_INC 0x0008
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#define LTQ_EIU_EXIN_INEN 0x000C
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-/* irq numbers used by the external interrupt unit (EIU) */
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-#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
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-#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
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-#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
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-#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
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-#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
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-#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
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-#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
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-#define XWAY_EXIN_COUNT 3
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+/* number of external interrupts */
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#define MAX_EIU 6
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/* the performance counter */
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@@ -72,20 +65,19 @@
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int gic_present;
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#endif
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-static unsigned short ltq_eiu_irq[MAX_EIU] = {
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- LTQ_EIU_IR0,
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- LTQ_EIU_IR1,
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- LTQ_EIU_IR2,
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- LTQ_EIU_IR3,
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- LTQ_EIU_IR4,
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- LTQ_EIU_IR5,
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-};
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-
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static int exin_avail;
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+static struct resource ltq_eiu_irq[MAX_EIU];
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static void __iomem *ltq_icu_membase[MAX_IM];
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static void __iomem *ltq_eiu_membase;
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static struct irq_domain *ltq_domain;
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+int ltq_eiu_get_irq(int exin)
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+{
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+ if (exin < exin_avail)
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+ return ltq_eiu_irq[exin].start;
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+ return -1;
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+}
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+
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void ltq_disable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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@@ -128,19 +120,64 @@ void ltq_enable_irq(struct irq_data *d)
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ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
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}
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+static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
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+{
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+ int i;
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+
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+ for (i = 0; i < MAX_EIU; i++) {
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+ if (d->hwirq == ltq_eiu_irq[i].start) {
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+ int val = 0;
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+ int edge = 0;
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+
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+ switch (type) {
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+ case IRQF_TRIGGER_NONE:
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+ break;
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+ case IRQF_TRIGGER_RISING:
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+ val = 1;
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+ edge = 1;
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+ break;
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+ case IRQF_TRIGGER_FALLING:
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+ val = 2;
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+ edge = 1;
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+ break;
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+ case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
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+ val = 3;
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+ edge = 1;
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+ break;
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+ case IRQF_TRIGGER_HIGH:
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+ val = 5;
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+ break;
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+ case IRQF_TRIGGER_LOW:
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+ val = 6;
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+ break;
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+ default:
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+ pr_err("invalid type %d for irq %ld\n", type, d->hwirq);
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+ return -EINVAL;
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+ }
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+
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+ if (edge)
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+ irq_set_handler(d->hwirq, handle_edge_irq);
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+
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+ ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
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+ (val << (i * 4)), LTQ_EIU_EXIN_C);
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
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{
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int i;
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ltq_enable_irq(d);
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for (i = 0; i < MAX_EIU; i++) {
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- if (d->hwirq == ltq_eiu_irq[i]) {
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- /* low level - we should really handle set_type */
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- ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
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- (0x6 << (i * 4)), LTQ_EIU_EXIN_C);
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+ if (d->hwirq == ltq_eiu_irq[i].start) {
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+ /* by default we are low level triggered */
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+ ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
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/* clear all pending */
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- ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
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- LTQ_EIU_EXIN_INIC);
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+ ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
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+ LTQ_EIU_EXIN_INC);
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/* enable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
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LTQ_EIU_EXIN_INEN);
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@@ -157,7 +194,7 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
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ltq_disable_irq(d);
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for (i = 0; i < MAX_EIU; i++) {
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- if (d->hwirq == ltq_eiu_irq[i]) {
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+ if (d->hwirq == ltq_eiu_irq[i].start) {
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/* disable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
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LTQ_EIU_EXIN_INEN);
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@@ -186,6 +223,7 @@ static struct irq_chip ltq_eiu_type = {
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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+ .irq_set_type = ltq_eiu_settype,
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};
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static void ltq_hw_irqdispatch(int module)
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@@ -301,7 +339,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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return 0;
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for (i = 0; i < exin_avail; i++)
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- if (hw == ltq_eiu_irq[i])
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+ if (hw == ltq_eiu_irq[i].start)
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chip = <q_eiu_type;
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irq_set_chip_and_handler(hw, chip, handle_level_irq);
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@@ -323,7 +361,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
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{
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struct device_node *eiu_node;
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struct resource res;
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- int i;
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+ int i, ret;
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for (i = 0; i < MAX_IM; i++) {
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if (of_address_to_resource(node, i, &res))
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@@ -340,17 +378,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
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}
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/* the external interrupts are optional and xway only */
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- eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
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+ eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
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if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
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/* find out how many external irq sources we have */
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- const __be32 *count = of_get_property(node,
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- "lantiq,count", NULL);
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+ exin_avail = of_irq_count(eiu_node);
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- if (count)
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- exin_avail = *count;
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if (exin_avail > MAX_EIU)
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exin_avail = MAX_EIU;
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+ ret = of_irq_to_resource_table(eiu_node,
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+ ltq_eiu_irq, exin_avail);
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+ if (ret != exin_avail)
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+ panic("failed to load external irq resources\n");
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+
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if (request_mem_region(res.start, resource_size(&res),
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res.name) < 0)
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pr_err("Failed to request eiu memory");
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--
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1.7.10.4
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