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61 lines
1.6 KiB
61 lines
1.6 KiB
There is a variant of MT7621 which contains only one CPU core instead of 2.
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This is not reflected in the config register, so the kernel detects more
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physical cores, which leads to a hang on SMP bringup.
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Add a hack to detect missing cores.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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--- a/arch/mips/kernel/smp-cps.c
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+++ b/arch/mips/kernel/smp-cps.c
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@@ -47,6 +47,11 @@ static unsigned core_vpe_count(unsigned
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return mips_cps_numvps(cluster, core);
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}
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+bool __weak plat_cpu_core_present(int core)
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+{
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+ return true;
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+}
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+
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static void __init cps_smp_setup(void)
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{
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unsigned int nclusters, ncores, nvpes, core_vpes;
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@@ -64,6 +69,8 @@ static void __init cps_smp_setup(void)
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ncores = mips_cps_numcores(cl);
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for (c = 0; c < ncores; c++) {
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+ if (!plat_cpu_core_present(c))
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+ continue;
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core_vpes = core_vpe_count(cl, c);
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if (c > 0)
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -15,6 +15,7 @@
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#include <asm/mips-cps.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7621.h>
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+#include <asm/mips-boards/launch.h>
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#include <pinmux.h>
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@@ -162,6 +163,20 @@ void __init ralink_of_remap(void)
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panic("Failed to remap core resources");
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}
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+bool plat_cpu_core_present(int core)
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+{
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+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
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+
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+ if (!core)
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+ return true;
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+ launch += core * 2; /* 2 VPEs per core */
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+ if (!(launch->flags & LAUNCH_FREADY))
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+ return false;
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+ if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE))
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+ return false;
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+ return true;
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+}
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+
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
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