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92 lines
3.3 KiB
92 lines
3.3 KiB
From 61c40f35f5cd6f67ccbd7319a1722eb78c815989 Mon Sep 17 00:00:00 2001
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From: Gregory CLEMENT <gregory.clement@bootlin.com>
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Date: Tue, 19 Jun 2018 14:34:45 +0200
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Subject: [PATCH] clk: mvebu: armada-37xx-periph: Fix switching CPU rate from
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300Mhz to 1.2GHz
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Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
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respectively) to L0 frequency (1.2 Ghz) requires a significant amount
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of time to let VDD stabilize to the appropriate voltage. This amount of
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time is large enough that it cannot be covered by the hardware
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countdown register. Due to this, the CPU might start operating at L0
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before the voltage is stabilized, leading to CPU stalls.
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To work around this problem, we prevent switching directly from the
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L2/L3 frequencies to the L0 frequency, and instead switch to the L1
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frequency in-between. The sequence therefore becomes:
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1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
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2. Sleep 20ms for stabling VDD voltage
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3. Then switch from L1(600MHZ) to L0(1200Mhz).
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It is based on the work done by Ken Ma <make@marvell.com>
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Cc: stable@vger.kernel.org
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Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks")
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/mvebu/armada-37xx-periph.c | 38 ++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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--- a/drivers/clk/mvebu/armada-37xx-periph.c
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+++ b/drivers/clk/mvebu/armada-37xx-periph.c
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@@ -35,6 +35,7 @@
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#define CLK_SEL 0x10
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#define CLK_DIS 0x14
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+#define ARMADA_37XX_DVFS_LOAD_1 1
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#define LOAD_LEVEL_NR 4
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#define ARMADA_37XX_NB_L0L1 0x18
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@@ -507,6 +508,40 @@ static long clk_pm_cpu_round_rate(struct
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return -EINVAL;
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}
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+/*
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+ * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
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+ * respectively) to L0 frequency (1.2 Ghz) requires a significant
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+ * amount of time to let VDD stabilize to the appropriate
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+ * voltage. This amount of time is large enough that it cannot be
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+ * covered by the hardware countdown register. Due to this, the CPU
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+ * might start operating at L0 before the voltage is stabilized,
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+ * leading to CPU stalls.
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+ *
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+ * To work around this problem, we prevent switching directly from the
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+ * L2/L3 frequencies to the L0 frequency, and instead switch to the L1
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+ * frequency in-between. The sequence therefore becomes:
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+ * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
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+ * 2. Sleep 20ms for stabling VDD voltage
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+ * 3. Then switch from L1(600MHZ) to L0(1200Mhz).
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+ */
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+static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
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+{
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+ unsigned int cur_level;
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+
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+ if (rate != 1200 * 1000 * 1000)
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+ return;
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+
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+ regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
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+ cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
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+ if (cur_level <= ARMADA_37XX_DVFS_LOAD_1)
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+ return;
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+
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+ regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
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+ ARMADA_37XX_NB_CPU_LOAD_MASK,
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+ ARMADA_37XX_DVFS_LOAD_1);
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+ msleep(20);
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+}
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+
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static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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@@ -537,6 +572,9 @@ static int clk_pm_cpu_set_rate(struct cl
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*/
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reg = ARMADA_37XX_NB_CPU_LOAD;
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mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
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+
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+ clk_pm_cpu_set_rate_wa(rate, base);
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+
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regmap_update_bits(base, reg, mask, load_level);
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return rate;
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