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1131 lines
24 KiB
1131 lines
24 KiB
/*
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* Atheros AR71xx SoC platform devices
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/clk.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/irq.h>
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#include "common.h"
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#include "dev-eth.h"
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unsigned char ath79_mac_base[ETH_ALEN] __initdata;
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static struct resource ath79_mdio0_resources[] = {
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{
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.name = "mdio_base",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_GE0_BASE,
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.end = AR71XX_GE0_BASE + 0x200 - 1,
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}
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};
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static struct ag71xx_mdio_platform_data ath79_mdio0_data;
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struct platform_device ath79_mdio0_device = {
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.name = "ag71xx-mdio",
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.id = 0,
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.resource = ath79_mdio0_resources,
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.num_resources = ARRAY_SIZE(ath79_mdio0_resources),
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.dev = {
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.platform_data = &ath79_mdio0_data,
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},
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};
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static struct resource ath79_mdio1_resources[] = {
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{
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.name = "mdio_base",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_GE1_BASE,
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.end = AR71XX_GE1_BASE + 0x200 - 1,
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}
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};
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static struct ag71xx_mdio_platform_data ath79_mdio1_data;
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struct platform_device ath79_mdio1_device = {
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.name = "ag71xx-mdio",
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.id = 1,
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.resource = ath79_mdio1_resources,
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.num_resources = ARRAY_SIZE(ath79_mdio1_resources),
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.dev = {
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.platform_data = &ath79_mdio1_data,
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},
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};
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static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
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{
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void __iomem *base;
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u32 t;
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base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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t = __raw_readl(base + cfg_reg);
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t &= ~(3 << shift);
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t |= (2 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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__raw_writel(pll_val, base + pll_reg);
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t |= (3 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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t &= ~(3 << shift);
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__raw_writel(t, base + cfg_reg);
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udelay(100);
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printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
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(unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
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iounmap(base);
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}
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static void __init ath79_mii_ctrl_set_if(unsigned int reg,
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unsigned int mii_if)
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{
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void __iomem *base;
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u32 t;
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base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
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t = __raw_readl(base + reg);
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t &= ~(AR71XX_MII_CTRL_IF_MASK);
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t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
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__raw_writel(t, base + reg);
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iounmap(base);
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}
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static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
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{
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void __iomem *base;
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unsigned int mii_speed;
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u32 t;
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switch (speed) {
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case SPEED_10:
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mii_speed = AR71XX_MII_CTRL_SPEED_10;
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break;
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case SPEED_100:
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mii_speed = AR71XX_MII_CTRL_SPEED_100;
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break;
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case SPEED_1000:
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mii_speed = AR71XX_MII_CTRL_SPEED_1000;
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break;
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default:
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BUG();
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}
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base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
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t = __raw_readl(base + reg);
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t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
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t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
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__raw_writel(t, base + reg);
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iounmap(base);
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}
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static unsigned long ar934x_get_mdio_ref_clock(void)
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{
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void __iomem *base;
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unsigned long ret;
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u32 t;
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base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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ret = 0;
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t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
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ret = 100 * 1000 * 1000;
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} else {
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struct clk *clk;
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clk = clk_get(NULL, "ref");
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if (!IS_ERR(clk))
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ret = clk_get_rate(clk);
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}
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iounmap(base);
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return ret;
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}
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void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
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{
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struct platform_device *mdio_dev;
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struct ag71xx_mdio_platform_data *mdio_data;
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unsigned int max_id;
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if (ath79_soc == ATH79_SOC_AR9341 ||
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ath79_soc == ATH79_SOC_AR9342 ||
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ath79_soc == ATH79_SOC_AR9344 ||
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ath79_soc == ATH79_SOC_QCA9556 ||
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ath79_soc == ATH79_SOC_QCA9558)
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max_id = 1;
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else
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max_id = 0;
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if (id > max_id) {
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printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
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return;
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}
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switch (ath79_soc) {
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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mdio_dev = &ath79_mdio1_device;
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mdio_data = &ath79_mdio1_data;
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break;
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case ATH79_SOC_AR9341:
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case ATH79_SOC_AR9342:
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case ATH79_SOC_AR9344:
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case ATH79_SOC_QCA9556:
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case ATH79_SOC_QCA9558:
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if (id == 0) {
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mdio_dev = &ath79_mdio0_device;
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mdio_data = &ath79_mdio0_data;
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} else {
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mdio_dev = &ath79_mdio1_device;
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mdio_data = &ath79_mdio1_data;
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}
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break;
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case ATH79_SOC_AR7242:
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ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
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AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
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AR71XX_ETH0_PLL_SHIFT);
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/* fall through */
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default:
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mdio_dev = &ath79_mdio0_device;
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mdio_data = &ath79_mdio0_data;
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break;
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}
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mdio_data->phy_mask = phy_mask;
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switch (ath79_soc) {
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case ATH79_SOC_AR7240:
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mdio_data->is_ar7240 = 1;
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/* fall through */
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case ATH79_SOC_AR7241:
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mdio_data->builtin_switch = 1;
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break;
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case ATH79_SOC_AR9330:
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mdio_data->is_ar9330 = 1;
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/* fall through */
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case ATH79_SOC_AR9331:
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mdio_data->builtin_switch = 1;
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break;
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case ATH79_SOC_AR9341:
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case ATH79_SOC_AR9342:
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case ATH79_SOC_AR9344:
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if (id == 1) {
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mdio_data->builtin_switch = 1;
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mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
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mdio_data->mdio_clock = 6250000;
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}
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mdio_data->is_ar934x = 1;
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break;
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case ATH79_SOC_QCA9558:
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if (id == 1)
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mdio_data->builtin_switch = 1;
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mdio_data->is_ar934x = 1;
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break;
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case ATH79_SOC_QCA9556:
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mdio_data->is_ar934x = 1;
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break;
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default:
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break;
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}
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platform_device_register(mdio_dev);
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}
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struct ath79_eth_pll_data ath79_eth0_pll_data;
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struct ath79_eth_pll_data ath79_eth1_pll_data;
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static u32 ath79_get_eth_pll(unsigned int mac, int speed)
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{
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struct ath79_eth_pll_data *pll_data;
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u32 pll_val;
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switch (mac) {
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case 0:
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pll_data = &ath79_eth0_pll_data;
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break;
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case 1:
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pll_data = &ath79_eth1_pll_data;
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break;
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default:
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BUG();
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}
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switch (speed) {
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case SPEED_10:
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pll_val = pll_data->pll_10;
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break;
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case SPEED_100:
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pll_val = pll_data->pll_100;
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break;
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case SPEED_1000:
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pll_val = pll_data->pll_1000;
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break;
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default:
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BUG();
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}
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return pll_val;
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}
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static void ath79_set_speed_ge0(int speed)
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{
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u32 val = ath79_get_eth_pll(0, speed);
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ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
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val, AR71XX_ETH0_PLL_SHIFT);
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ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
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}
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static void ath79_set_speed_ge1(int speed)
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{
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u32 val = ath79_get_eth_pll(1, speed);
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ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
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val, AR71XX_ETH1_PLL_SHIFT);
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ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
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}
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static void ar7242_set_speed_ge0(int speed)
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{
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u32 val = ath79_get_eth_pll(0, speed);
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void __iomem *base;
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base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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__raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
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iounmap(base);
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}
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static void ar91xx_set_speed_ge0(int speed)
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{
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u32 val = ath79_get_eth_pll(0, speed);
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ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
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val, AR913X_ETH0_PLL_SHIFT);
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ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
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}
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static void ar91xx_set_speed_ge1(int speed)
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{
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u32 val = ath79_get_eth_pll(1, speed);
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ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
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val, AR913X_ETH1_PLL_SHIFT);
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ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
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}
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static void ar934x_set_speed_ge0(int speed)
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{
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void __iomem *base;
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u32 val = ath79_get_eth_pll(0, speed);
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base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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__raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
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iounmap(base);
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}
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static void qca955x_set_speed_xmii(int speed)
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{
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void __iomem *base;
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u32 val = ath79_get_eth_pll(0, speed);
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base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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__raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
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iounmap(base);
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}
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static void qca955x_set_speed_sgmii(int speed)
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{
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void __iomem *base;
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u32 val = ath79_get_eth_pll(1, speed);
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base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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__raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
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iounmap(base);
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}
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static void ath79_set_speed_dummy(int speed)
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{
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}
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static void ath79_ddr_no_flush(void)
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{
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}
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static void ath79_ddr_flush_ge0(void)
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{
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ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
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}
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static void ath79_ddr_flush_ge1(void)
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{
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ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
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}
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static void ar724x_ddr_flush_ge0(void)
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{
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ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
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}
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static void ar724x_ddr_flush_ge1(void)
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{
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ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
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}
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static void ar91xx_ddr_flush_ge0(void)
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{
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ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
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}
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static void ar91xx_ddr_flush_ge1(void)
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{
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ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
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}
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static void ar933x_ddr_flush_ge0(void)
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{
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ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
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}
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static void ar933x_ddr_flush_ge1(void)
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{
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ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
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}
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static struct resource ath79_eth0_resources[] = {
|
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{
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.name = "mac_base",
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.flags = IORESOURCE_MEM,
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.start = AR71XX_GE0_BASE,
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.end = AR71XX_GE0_BASE + 0x200 - 1,
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}, {
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.name = "mac_irq",
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.flags = IORESOURCE_IRQ,
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.start = ATH79_CPU_IRQ(4),
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.end = ATH79_CPU_IRQ(4),
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},
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};
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struct ag71xx_platform_data ath79_eth0_data = {
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.reset_bit = AR71XX_RESET_GE0_MAC,
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};
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struct platform_device ath79_eth0_device = {
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.name = "ag71xx",
|
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.id = 0,
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.resource = ath79_eth0_resources,
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.num_resources = ARRAY_SIZE(ath79_eth0_resources),
|
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.dev = {
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.platform_data = &ath79_eth0_data,
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},
|
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};
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|
|
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static struct resource ath79_eth1_resources[] = {
|
|
{
|
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.name = "mac_base",
|
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.flags = IORESOURCE_MEM,
|
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.start = AR71XX_GE1_BASE,
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|
.end = AR71XX_GE1_BASE + 0x200 - 1,
|
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}, {
|
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.name = "mac_irq",
|
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.flags = IORESOURCE_IRQ,
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.start = ATH79_CPU_IRQ(5),
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.end = ATH79_CPU_IRQ(5),
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},
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};
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|
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struct ag71xx_platform_data ath79_eth1_data = {
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.reset_bit = AR71XX_RESET_GE1_MAC,
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};
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|
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struct platform_device ath79_eth1_device = {
|
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.name = "ag71xx",
|
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.id = 1,
|
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.resource = ath79_eth1_resources,
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.num_resources = ARRAY_SIZE(ath79_eth1_resources),
|
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.dev = {
|
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.platform_data = &ath79_eth1_data,
|
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},
|
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};
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|
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struct ag71xx_switch_platform_data ath79_switch_data;
|
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|
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#define AR71XX_PLL_VAL_1000 0x00110000
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#define AR71XX_PLL_VAL_100 0x00001099
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#define AR71XX_PLL_VAL_10 0x00991099
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|
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#define AR724X_PLL_VAL_1000 0x00110000
|
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#define AR724X_PLL_VAL_100 0x00001099
|
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#define AR724X_PLL_VAL_10 0x00991099
|
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|
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#define AR7242_PLL_VAL_1000 0x16000000
|
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#define AR7242_PLL_VAL_100 0x00000101
|
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#define AR7242_PLL_VAL_10 0x00001616
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|
|
#define AR913X_PLL_VAL_1000 0x1a000000
|
|
#define AR913X_PLL_VAL_100 0x13000a44
|
|
#define AR913X_PLL_VAL_10 0x00441099
|
|
|
|
#define AR933X_PLL_VAL_1000 0x00110000
|
|
#define AR933X_PLL_VAL_100 0x00001099
|
|
#define AR933X_PLL_VAL_10 0x00991099
|
|
|
|
#define AR934X_PLL_VAL_1000 0x16000000
|
|
#define AR934X_PLL_VAL_100 0x00000101
|
|
#define AR934X_PLL_VAL_10 0x00001616
|
|
|
|
static void __init ath79_init_eth_pll_data(unsigned int id)
|
|
{
|
|
struct ath79_eth_pll_data *pll_data;
|
|
u32 pll_10, pll_100, pll_1000;
|
|
|
|
switch (id) {
|
|
case 0:
|
|
pll_data = &ath79_eth0_pll_data;
|
|
break;
|
|
case 1:
|
|
pll_data = &ath79_eth1_pll_data;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
switch (ath79_soc) {
|
|
case ATH79_SOC_AR7130:
|
|
case ATH79_SOC_AR7141:
|
|
case ATH79_SOC_AR7161:
|
|
pll_10 = AR71XX_PLL_VAL_10;
|
|
pll_100 = AR71XX_PLL_VAL_100;
|
|
pll_1000 = AR71XX_PLL_VAL_1000;
|
|
break;
|
|
|
|
case ATH79_SOC_AR7240:
|
|
case ATH79_SOC_AR7241:
|
|
pll_10 = AR724X_PLL_VAL_10;
|
|
pll_100 = AR724X_PLL_VAL_100;
|
|
pll_1000 = AR724X_PLL_VAL_1000;
|
|
break;
|
|
|
|
case ATH79_SOC_AR7242:
|
|
pll_10 = AR7242_PLL_VAL_10;
|
|
pll_100 = AR7242_PLL_VAL_100;
|
|
pll_1000 = AR7242_PLL_VAL_1000;
|
|
break;
|
|
|
|
case ATH79_SOC_AR9130:
|
|
case ATH79_SOC_AR9132:
|
|
pll_10 = AR913X_PLL_VAL_10;
|
|
pll_100 = AR913X_PLL_VAL_100;
|
|
pll_1000 = AR913X_PLL_VAL_1000;
|
|
break;
|
|
|
|
case ATH79_SOC_AR9330:
|
|
case ATH79_SOC_AR9331:
|
|
pll_10 = AR933X_PLL_VAL_10;
|
|
pll_100 = AR933X_PLL_VAL_100;
|
|
pll_1000 = AR933X_PLL_VAL_1000;
|
|
break;
|
|
|
|
case ATH79_SOC_AR9341:
|
|
case ATH79_SOC_AR9342:
|
|
case ATH79_SOC_AR9344:
|
|
case ATH79_SOC_QCA9556:
|
|
case ATH79_SOC_QCA9558:
|
|
pll_10 = AR934X_PLL_VAL_10;
|
|
pll_100 = AR934X_PLL_VAL_100;
|
|
pll_1000 = AR934X_PLL_VAL_1000;
|
|
break;
|
|
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
if (!pll_data->pll_10)
|
|
pll_data->pll_10 = pll_10;
|
|
|
|
if (!pll_data->pll_100)
|
|
pll_data->pll_100 = pll_100;
|
|
|
|
if (!pll_data->pll_1000)
|
|
pll_data->pll_1000 = pll_1000;
|
|
}
|
|
|
|
static int __init ath79_setup_phy_if_mode(unsigned int id,
|
|
struct ag71xx_platform_data *pdata)
|
|
{
|
|
unsigned int mii_if;
|
|
|
|
switch (id) {
|
|
case 0:
|
|
switch (ath79_soc) {
|
|
case ATH79_SOC_AR7130:
|
|
case ATH79_SOC_AR7141:
|
|
case ATH79_SOC_AR7161:
|
|
case ATH79_SOC_AR9130:
|
|
case ATH79_SOC_AR9132:
|
|
switch (pdata->phy_if_mode) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
mii_if = AR71XX_MII0_CTRL_IF_MII;
|
|
break;
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
mii_if = AR71XX_MII0_CTRL_IF_GMII;
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
mii_if = AR71XX_MII0_CTRL_IF_RGMII;
|
|
break;
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
mii_if = AR71XX_MII0_CTRL_IF_RMII;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
|
|
break;
|
|
|
|
case ATH79_SOC_AR7240:
|
|
case ATH79_SOC_AR7241:
|
|
case ATH79_SOC_AR9330:
|
|
case ATH79_SOC_AR9331:
|
|
pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
|
|
break;
|
|
|
|
case ATH79_SOC_AR7242:
|
|
/* FIXME */
|
|
|
|
case ATH79_SOC_AR9341:
|
|
case ATH79_SOC_AR9342:
|
|
case ATH79_SOC_AR9344:
|
|
switch (pdata->phy_if_mode) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case ATH79_SOC_QCA9556:
|
|
case ATH79_SOC_QCA9558:
|
|
switch (pdata->phy_if_mode) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
BUG();
|
|
}
|
|
break;
|
|
case 1:
|
|
switch (ath79_soc) {
|
|
case ATH79_SOC_AR7130:
|
|
case ATH79_SOC_AR7141:
|
|
case ATH79_SOC_AR7161:
|
|
case ATH79_SOC_AR9130:
|
|
case ATH79_SOC_AR9132:
|
|
switch (pdata->phy_if_mode) {
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
mii_if = AR71XX_MII1_CTRL_IF_RMII;
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
mii_if = AR71XX_MII1_CTRL_IF_RGMII;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
|
|
break;
|
|
|
|
case ATH79_SOC_AR7240:
|
|
case ATH79_SOC_AR7241:
|
|
case ATH79_SOC_AR9330:
|
|
case ATH79_SOC_AR9331:
|
|
pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
|
|
break;
|
|
|
|
case ATH79_SOC_AR7242:
|
|
/* FIXME */
|
|
|
|
case ATH79_SOC_AR9341:
|
|
case ATH79_SOC_AR9342:
|
|
case ATH79_SOC_AR9344:
|
|
switch (pdata->phy_if_mode) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case ATH79_SOC_QCA9556:
|
|
case ATH79_SOC_QCA9558:
|
|
switch (pdata->phy_if_mode) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
BUG();
|
|
}
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
|
|
{
|
|
void __iomem *base;
|
|
u32 t;
|
|
|
|
base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
|
|
|
|
t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
|
|
t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
|
|
if (mac)
|
|
t |= AR933X_ETH_CFG_SW_PHY_SWAP;
|
|
if (mdio)
|
|
t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
|
|
__raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
|
|
|
|
iounmap(base);
|
|
}
|
|
|
|
void __init ath79_setup_ar934x_eth_cfg(u32 mask)
|
|
{
|
|
void __iomem *base;
|
|
u32 t;
|
|
|
|
base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
|
|
|
|
t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
|
|
|
|
t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
|
|
AR934X_ETH_CFG_MII_GMAC0 |
|
|
AR934X_ETH_CFG_GMII_GMAC0 |
|
|
AR934X_ETH_CFG_SW_ONLY_MODE |
|
|
AR934X_ETH_CFG_SW_PHY_SWAP);
|
|
|
|
t |= mask;
|
|
|
|
__raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
|
|
/* flush write */
|
|
__raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
|
|
|
|
iounmap(base);
|
|
}
|
|
|
|
static int ath79_eth_instance __initdata;
|
|
void __init ath79_register_eth(unsigned int id)
|
|
{
|
|
struct platform_device *pdev;
|
|
struct ag71xx_platform_data *pdata;
|
|
int err;
|
|
|
|
if (id > 1) {
|
|
printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
|
|
return;
|
|
}
|
|
|
|
ath79_init_eth_pll_data(id);
|
|
|
|
if (id == 0)
|
|
pdev = &ath79_eth0_device;
|
|
else
|
|
pdev = &ath79_eth1_device;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
err = ath79_setup_phy_if_mode(id, pdata);
|
|
if (err) {
|
|
printk(KERN_ERR
|
|
"ar71xx: invalid PHY interface mode for GE%u\n", id);
|
|
return;
|
|
}
|
|
|
|
switch (ath79_soc) {
|
|
case ATH79_SOC_AR7130:
|
|
if (id == 0) {
|
|
pdata->ddr_flush = ath79_ddr_flush_ge0;
|
|
pdata->set_speed = ath79_set_speed_ge0;
|
|
} else {
|
|
pdata->ddr_flush = ath79_ddr_flush_ge1;
|
|
pdata->set_speed = ath79_set_speed_ge1;
|
|
}
|
|
break;
|
|
|
|
case ATH79_SOC_AR7141:
|
|
case ATH79_SOC_AR7161:
|
|
if (id == 0) {
|
|
pdata->ddr_flush = ath79_ddr_flush_ge0;
|
|
pdata->set_speed = ath79_set_speed_ge0;
|
|
} else {
|
|
pdata->ddr_flush = ath79_ddr_flush_ge1;
|
|
pdata->set_speed = ath79_set_speed_ge1;
|
|
}
|
|
pdata->has_gbit = 1;
|
|
break;
|
|
|
|
case ATH79_SOC_AR7242:
|
|
if (id == 0) {
|
|
pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
|
|
AR71XX_RESET_GE0_PHY;
|
|
pdata->ddr_flush = ar724x_ddr_flush_ge0;
|
|
pdata->set_speed = ar7242_set_speed_ge0;
|
|
} else {
|
|
pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
|
|
AR71XX_RESET_GE1_PHY;
|
|
pdata->ddr_flush = ar724x_ddr_flush_ge1;
|
|
pdata->set_speed = ath79_set_speed_dummy;
|
|
}
|
|
pdata->has_gbit = 1;
|
|
pdata->is_ar724x = 1;
|
|
|
|
if (!pdata->fifo_cfg1)
|
|
pdata->fifo_cfg1 = 0x0010ffff;
|
|
if (!pdata->fifo_cfg2)
|
|
pdata->fifo_cfg2 = 0x015500aa;
|
|
if (!pdata->fifo_cfg3)
|
|
pdata->fifo_cfg3 = 0x01f00140;
|
|
break;
|
|
|
|
case ATH79_SOC_AR7241:
|
|
if (id == 0)
|
|
pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
|
|
else
|
|
pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
|
|
/* fall through */
|
|
case ATH79_SOC_AR7240:
|
|
if (id == 0) {
|
|
pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
|
|
pdata->ddr_flush = ar724x_ddr_flush_ge0;
|
|
pdata->set_speed = ath79_set_speed_dummy;
|
|
|
|
pdata->phy_mask = BIT(4);
|
|
} else {
|
|
pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
|
|
pdata->ddr_flush = ar724x_ddr_flush_ge1;
|
|
pdata->set_speed = ath79_set_speed_dummy;
|
|
|
|
pdata->speed = SPEED_1000;
|
|
pdata->duplex = DUPLEX_FULL;
|
|
pdata->switch_data = &ath79_switch_data;
|
|
|
|
ath79_switch_data.phy_poll_mask |= BIT(4);
|
|
}
|
|
pdata->has_gbit = 1;
|
|
pdata->is_ar724x = 1;
|
|
if (ath79_soc == ATH79_SOC_AR7240)
|
|
pdata->is_ar7240 = 1;
|
|
|
|
if (!pdata->fifo_cfg1)
|
|
pdata->fifo_cfg1 = 0x0010ffff;
|
|
if (!pdata->fifo_cfg2)
|
|
pdata->fifo_cfg2 = 0x015500aa;
|
|
if (!pdata->fifo_cfg3)
|
|
pdata->fifo_cfg3 = 0x01f00140;
|
|
break;
|
|
|
|
case ATH79_SOC_AR9130:
|
|
if (id == 0) {
|
|
pdata->ddr_flush = ar91xx_ddr_flush_ge0;
|
|
pdata->set_speed = ar91xx_set_speed_ge0;
|
|
} else {
|
|
pdata->ddr_flush = ar91xx_ddr_flush_ge1;
|
|
pdata->set_speed = ar91xx_set_speed_ge1;
|
|
}
|
|
pdata->is_ar91xx = 1;
|
|
break;
|
|
|
|
case ATH79_SOC_AR9132:
|
|
if (id == 0) {
|
|
pdata->ddr_flush = ar91xx_ddr_flush_ge0;
|
|
pdata->set_speed = ar91xx_set_speed_ge0;
|
|
} else {
|
|
pdata->ddr_flush = ar91xx_ddr_flush_ge1;
|
|
pdata->set_speed = ar91xx_set_speed_ge1;
|
|
}
|
|
pdata->is_ar91xx = 1;
|
|
pdata->has_gbit = 1;
|
|
break;
|
|
|
|
case ATH79_SOC_AR9330:
|
|
case ATH79_SOC_AR9331:
|
|
if (id == 0) {
|
|
pdata->reset_bit = AR933X_RESET_GE0_MAC |
|
|
AR933X_RESET_GE0_MDIO;
|
|
pdata->ddr_flush = ar933x_ddr_flush_ge0;
|
|
pdata->set_speed = ath79_set_speed_dummy;
|
|
|
|
pdata->phy_mask = BIT(4);
|
|
} else {
|
|
pdata->reset_bit = AR933X_RESET_GE1_MAC |
|
|
AR933X_RESET_GE1_MDIO;
|
|
pdata->ddr_flush = ar933x_ddr_flush_ge1;
|
|
pdata->set_speed = ath79_set_speed_dummy;
|
|
|
|
pdata->speed = SPEED_1000;
|
|
pdata->duplex = DUPLEX_FULL;
|
|
pdata->switch_data = &ath79_switch_data;
|
|
|
|
ath79_switch_data.phy_poll_mask |= BIT(4);
|
|
}
|
|
|
|
pdata->has_gbit = 1;
|
|
pdata->is_ar724x = 1;
|
|
|
|
if (!pdata->fifo_cfg1)
|
|
pdata->fifo_cfg1 = 0x0010ffff;
|
|
if (!pdata->fifo_cfg2)
|
|
pdata->fifo_cfg2 = 0x015500aa;
|
|
if (!pdata->fifo_cfg3)
|
|
pdata->fifo_cfg3 = 0x01f00140;
|
|
break;
|
|
|
|
case ATH79_SOC_AR9341:
|
|
case ATH79_SOC_AR9342:
|
|
case ATH79_SOC_AR9344:
|
|
if (id == 0) {
|
|
pdata->reset_bit = AR934X_RESET_GE0_MAC |
|
|
AR934X_RESET_GE0_MDIO;
|
|
pdata->set_speed = ar934x_set_speed_ge0;
|
|
} else {
|
|
pdata->reset_bit = AR934X_RESET_GE1_MAC |
|
|
AR934X_RESET_GE1_MDIO;
|
|
pdata->set_speed = ath79_set_speed_dummy;
|
|
|
|
pdata->switch_data = &ath79_switch_data;
|
|
|
|
/* reset the built-in switch */
|
|
ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
|
|
ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
|
|
}
|
|
|
|
pdata->ddr_flush = ath79_ddr_no_flush;
|
|
pdata->has_gbit = 1;
|
|
pdata->is_ar724x = 1;
|
|
|
|
if (!pdata->fifo_cfg1)
|
|
pdata->fifo_cfg1 = 0x0010ffff;
|
|
if (!pdata->fifo_cfg2)
|
|
pdata->fifo_cfg2 = 0x015500aa;
|
|
if (!pdata->fifo_cfg3)
|
|
pdata->fifo_cfg3 = 0x01f00140;
|
|
break;
|
|
|
|
case ATH79_SOC_QCA9556:
|
|
case ATH79_SOC_QCA9558:
|
|
if (id == 0) {
|
|
pdata->reset_bit = QCA955X_RESET_GE0_MAC |
|
|
QCA955X_RESET_GE0_MDIO;
|
|
pdata->set_speed = qca955x_set_speed_xmii;
|
|
} else {
|
|
pdata->reset_bit = QCA955X_RESET_GE1_MAC |
|
|
QCA955X_RESET_GE1_MDIO;
|
|
pdata->set_speed = qca955x_set_speed_sgmii;
|
|
}
|
|
|
|
pdata->ddr_flush = ath79_ddr_no_flush;
|
|
pdata->has_gbit = 1;
|
|
pdata->is_ar724x = 1;
|
|
|
|
if (!pdata->fifo_cfg1)
|
|
pdata->fifo_cfg1 = 0x0010ffff;
|
|
if (!pdata->fifo_cfg2)
|
|
pdata->fifo_cfg2 = 0x015500aa;
|
|
if (!pdata->fifo_cfg3)
|
|
pdata->fifo_cfg3 = 0x01f00140;
|
|
break;
|
|
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
switch (pdata->phy_if_mode) {
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
if (!pdata->has_gbit) {
|
|
printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
|
|
id);
|
|
return;
|
|
}
|
|
/* fallthrough */
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (!is_valid_ether_addr(pdata->mac_addr)) {
|
|
random_ether_addr(pdata->mac_addr);
|
|
printk(KERN_DEBUG
|
|
"ar71xx: using random MAC address for eth%d\n",
|
|
ath79_eth_instance);
|
|
}
|
|
|
|
if (pdata->mii_bus_dev == NULL) {
|
|
switch (ath79_soc) {
|
|
case ATH79_SOC_AR9341:
|
|
case ATH79_SOC_AR9342:
|
|
case ATH79_SOC_AR9344:
|
|
if (id == 0)
|
|
pdata->mii_bus_dev = &ath79_mdio0_device.dev;
|
|
else
|
|
pdata->mii_bus_dev = &ath79_mdio1_device.dev;
|
|
break;
|
|
|
|
case ATH79_SOC_AR7241:
|
|
case ATH79_SOC_AR9330:
|
|
case ATH79_SOC_AR9331:
|
|
pdata->mii_bus_dev = &ath79_mdio1_device.dev;
|
|
break;
|
|
|
|
case ATH79_SOC_QCA9556:
|
|
case ATH79_SOC_QCA9558:
|
|
/* don't assign any MDIO device by default */
|
|
break;
|
|
|
|
default:
|
|
pdata->mii_bus_dev = &ath79_mdio0_device.dev;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Reset the device */
|
|
ath79_device_reset_set(pdata->reset_bit);
|
|
mdelay(100);
|
|
|
|
ath79_device_reset_clear(pdata->reset_bit);
|
|
mdelay(100);
|
|
|
|
platform_device_register(pdev);
|
|
ath79_eth_instance++;
|
|
}
|
|
|
|
void __init ath79_set_mac_base(unsigned char *mac)
|
|
{
|
|
memcpy(ath79_mac_base, mac, ETH_ALEN);
|
|
}
|
|
|
|
void __init ath79_parse_mac_addr(char *mac_str)
|
|
{
|
|
u8 tmp[ETH_ALEN];
|
|
int t;
|
|
|
|
t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
|
|
&tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
|
|
|
|
if (t != ETH_ALEN)
|
|
t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
|
|
&tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
|
|
|
|
if (t == ETH_ALEN)
|
|
ath79_set_mac_base(tmp);
|
|
else
|
|
printk(KERN_DEBUG "ar71xx: failed to parse mac address "
|
|
"\"%s\"\n", mac_str);
|
|
}
|
|
|
|
static int __init ath79_ethaddr_setup(char *str)
|
|
{
|
|
ath79_parse_mac_addr(str);
|
|
return 1;
|
|
}
|
|
__setup("ethaddr=", ath79_ethaddr_setup);
|
|
|
|
static int __init ath79_kmac_setup(char *str)
|
|
{
|
|
ath79_parse_mac_addr(str);
|
|
return 1;
|
|
}
|
|
__setup("kmac=", ath79_kmac_setup);
|
|
|
|
void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
|
|
int offset)
|
|
{
|
|
int t;
|
|
|
|
if (!dst)
|
|
return;
|
|
|
|
if (!src || !is_valid_ether_addr(src)) {
|
|
memset(dst, '\0', ETH_ALEN);
|
|
return;
|
|
}
|
|
|
|
t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
|
|
t += offset;
|
|
|
|
dst[0] = src[0];
|
|
dst[1] = src[1];
|
|
dst[2] = src[2];
|
|
dst[3] = (t >> 16) & 0xff;
|
|
dst[4] = (t >> 8) & 0xff;
|
|
dst[5] = t & 0xff;
|
|
}
|
|
|
|
void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
|
|
{
|
|
int i;
|
|
|
|
if (!dst)
|
|
return;
|
|
|
|
if (!src || !is_valid_ether_addr(src)) {
|
|
memset(dst, '\0', ETH_ALEN);
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < ETH_ALEN; i++)
|
|
dst[i] = src[i];
|
|
dst[0] |= 0x02;
|
|
}
|
|
|