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260 lines
6.9 KiB
260 lines
6.9 KiB
/* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <ralink_regs.h>
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#include "mtk_eth_soc.h"
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#include "gsw_mt7620.h"
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void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
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{
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iowrite32(val, gsw->base + reg);
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}
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u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
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{
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return ioread32(gsw->base + reg);
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}
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static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
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{
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struct fe_priv *priv = (struct fe_priv *)_priv;
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struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
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u32 status;
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int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
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status = mtk_switch_r32(gsw, GSW_REG_ISR);
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if (status & PORT_IRQ_ST_CHG)
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for (i = 0; i <= max; i++) {
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u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
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int link = status & 0x1;
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if (link != priv->link[i])
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mt7620_print_link_state(priv, i, link,
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(status >> 2) & 3,
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(status & 0x2));
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priv->link[i] = link;
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}
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mt7620_handle_carrier(priv);
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mtk_switch_w32(gsw, status, GSW_REG_ISR);
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return IRQ_HANDLED;
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}
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static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
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{
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u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
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rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
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mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
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/* Enable MIB stats */
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mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
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if (of_property_read_bool(np, "mediatek,mt7530")) {
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u32 val;
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/* turn off ephy and set phy base addr to 12 */
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mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
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(0x1f << 24) | (0xc << 16),
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GSW_REG_GPC1);
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/* set MT7530 central align */
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val = mt7530_mdio_r32(gsw, 0x7830);
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val &= ~BIT(0);
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val |= BIT(1);
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mt7530_mdio_w32(gsw, 0x7830, val);
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val = mt7530_mdio_r32(gsw, 0x7a40);
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val &= ~BIT(30);
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mt7530_mdio_w32(gsw, 0x7a40, val);
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mt7530_mdio_w32(gsw, 0x7a78, 0x855);
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} else {
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/* global page 4 */
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_mt7620_mii_write(gsw, 1, 31, 0x4000);
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_mt7620_mii_write(gsw, 1, 17, 0x7444);
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if (is_BGA)
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_mt7620_mii_write(gsw, 1, 19, 0x0114);
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else
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_mt7620_mii_write(gsw, 1, 19, 0x0117);
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_mt7620_mii_write(gsw, 1, 22, 0x10cf);
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_mt7620_mii_write(gsw, 1, 25, 0x6212);
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_mt7620_mii_write(gsw, 1, 26, 0x0777);
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_mt7620_mii_write(gsw, 1, 29, 0x4000);
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_mt7620_mii_write(gsw, 1, 28, 0xc077);
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_mt7620_mii_write(gsw, 1, 24, 0x0000);
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/* global page 3 */
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_mt7620_mii_write(gsw, 1, 31, 0x3000);
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_mt7620_mii_write(gsw, 1, 17, 0x4838);
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/* global page 2 */
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_mt7620_mii_write(gsw, 1, 31, 0x2000);
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if (is_BGA) {
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_mt7620_mii_write(gsw, 1, 21, 0x0515);
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_mt7620_mii_write(gsw, 1, 22, 0x0053);
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_mt7620_mii_write(gsw, 1, 23, 0x00bf);
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_mt7620_mii_write(gsw, 1, 24, 0x0aaf);
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_mt7620_mii_write(gsw, 1, 25, 0x0fad);
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_mt7620_mii_write(gsw, 1, 26, 0x0fc1);
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} else {
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_mt7620_mii_write(gsw, 1, 21, 0x0517);
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_mt7620_mii_write(gsw, 1, 22, 0x0fd2);
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_mt7620_mii_write(gsw, 1, 23, 0x00bf);
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_mt7620_mii_write(gsw, 1, 24, 0x0aab);
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_mt7620_mii_write(gsw, 1, 25, 0x00ae);
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_mt7620_mii_write(gsw, 1, 26, 0x0fff);
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}
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/* global page 1 */
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_mt7620_mii_write(gsw, 1, 31, 0x1000);
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_mt7620_mii_write(gsw, 1, 17, 0xe7f8);
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}
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/* global page 0 */
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_mt7620_mii_write(gsw, 1, 31, 0x8000);
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_mt7620_mii_write(gsw, 0, 30, 0xa000);
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_mt7620_mii_write(gsw, 1, 30, 0xa000);
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_mt7620_mii_write(gsw, 2, 30, 0xa000);
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_mt7620_mii_write(gsw, 3, 30, 0xa000);
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_mt7620_mii_write(gsw, 0, 4, 0x05e1);
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_mt7620_mii_write(gsw, 1, 4, 0x05e1);
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_mt7620_mii_write(gsw, 2, 4, 0x05e1);
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_mt7620_mii_write(gsw, 3, 4, 0x05e1);
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/* global page 2 */
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_mt7620_mii_write(gsw, 1, 31, 0xa000);
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_mt7620_mii_write(gsw, 0, 16, 0x1111);
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_mt7620_mii_write(gsw, 1, 16, 0x1010);
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_mt7620_mii_write(gsw, 2, 16, 0x1515);
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_mt7620_mii_write(gsw, 3, 16, 0x0f0f);
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/* CPU Port6 Force Link 1G, FC ON */
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mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
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/* Set Port 6 as CPU Port */
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mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
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/* setup port 4 */
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if (gsw->port4 == PORT4_EPHY) {
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u32 val = rt_sysc_r32(SYSC_REG_CFG1);
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val |= 3 << 14;
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rt_sysc_w32(val, SYSC_REG_CFG1);
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_mt7620_mii_write(gsw, 4, 30, 0xa000);
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_mt7620_mii_write(gsw, 4, 4, 0x05e1);
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_mt7620_mii_write(gsw, 4, 16, 0x1313);
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_mt7620_mii_write(gsw, 4, 0, 0x3100);
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pr_info("gsw: setting port4 to ephy mode\n");
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}
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}
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static const struct of_device_id mediatek_gsw_match[] = {
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{ .compatible = "mediatek,mt7620-gsw" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
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int mtk_gsw_init(struct fe_priv *priv)
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{
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struct device_node *np = priv->switch_np;
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struct platform_device *pdev = of_find_device_by_node(np);
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struct mt7620_gsw *gsw;
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if (!pdev)
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return -ENODEV;
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if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
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return -EINVAL;
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gsw = platform_get_drvdata(pdev);
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priv->soc->swpriv = gsw;
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mt7620_hw_init(gsw, np);
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if (gsw->irq) {
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request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
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"gsw", priv);
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mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
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}
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return 0;
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}
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static int mt7620_gsw_probe(struct platform_device *pdev)
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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const char *port4 = NULL;
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struct mt7620_gsw *gsw;
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struct device_node *np = pdev->dev.of_node;
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gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
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if (!gsw)
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return -ENOMEM;
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gsw->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gsw->base))
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return PTR_ERR(gsw->base);
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gsw->dev = &pdev->dev;
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of_property_read_string(np, "mediatek,port4", &port4);
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if (port4 && !strcmp(port4, "ephy"))
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gsw->port4 = PORT4_EPHY;
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else if (port4 && !strcmp(port4, "gmac"))
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gsw->port4 = PORT4_EXT;
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else
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gsw->port4 = PORT4_EPHY;
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gsw->irq = platform_get_irq(pdev, 0);
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platform_set_drvdata(pdev, gsw);
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return 0;
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}
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static int mt7620_gsw_remove(struct platform_device *pdev)
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{
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver gsw_driver = {
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.probe = mt7620_gsw_probe,
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.remove = mt7620_gsw_remove,
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.driver = {
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.name = "mt7620-gsw",
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.owner = THIS_MODULE,
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.of_match_table = mediatek_gsw_match,
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},
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};
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module_platform_driver(gsw_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
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MODULE_VERSION(MTK_FE_DRV_VERSION);
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