You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
27 lines
916 B
27 lines
916 B
From 54204ef3edbb1aa2390cabba61fe185a12cc39f0 Mon Sep 17 00:00:00 2001
|
|
From: Felix Fietkau <nbd@nbd.name>
|
|
Date: Tue, 6 Mar 2018 08:35:44 +0100
|
|
Subject: [PATCH 11/27] MIPS: ath79: fix register address in
|
|
ath79_ddr_wb_flush()
|
|
|
|
ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
|
|
need to be a multiple of 4.
|
|
|
|
Cc: Alban Bedel <albeu@free.fr>
|
|
Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
|
|
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
|
---
|
|
arch/mips/ath79/common.c | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
--- a/arch/mips/ath79/common.c
|
|
+++ b/arch/mips/ath79/common.c
|
|
@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
|
|
|
|
void ath79_ddr_wb_flush(u32 reg)
|
|
{
|
|
- void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
|
|
+ void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
|
|
|
|
/* Flush the DDR write buffer. */
|
|
__raw_writel(0x1, flush_reg);
|
|
|