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218 lines
4.9 KiB
218 lines
4.9 KiB
/*
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* Atheros AR71xx built-in ethernet mac driver
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on Atheros' AG7100 driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/of_mdio.h>
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#include "ag71xx.h"
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#define AG71XX_MDIO_RETRY 1000
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#define AG71XX_MDIO_DELAY 5
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static int bus_count;
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static int ag71xx_mdio_wait_busy(struct ag71xx *ag)
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{
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int i;
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for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
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u32 busy;
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udelay(AG71XX_MDIO_DELAY);
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regmap_read(ag->mii_regmap, AG71XX_REG_MII_IND, &busy);
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if (!busy)
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return 0;
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udelay(AG71XX_MDIO_DELAY);
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}
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pr_err("%s: MDIO operation timed out\n", ag->mii_bus->name);
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return -ETIMEDOUT;
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}
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int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
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{
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struct ag71xx *ag = bus->priv;
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int err;
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int ret;
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err = ag71xx_mdio_wait_busy(ag);
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if (err)
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return 0xffff;
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_ADDR,
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((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_READ);
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err = ag71xx_mdio_wait_busy(ag);
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if (err)
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return 0xffff;
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regmap_read(ag->mii_regmap, AG71XX_REG_MII_STATUS, &ret);
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ret &= 0xffff;
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
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DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
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return ret;
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}
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int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
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{
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struct ag71xx *ag = bus->priv;
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DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_ADDR,
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((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_CTRL, val);
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ag71xx_mdio_wait_busy(ag);
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return 0;
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}
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static int ar934x_mdio_clock_div(unsigned int rate)
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{
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if (rate == 100 * 1000 * 1000)
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return 6; /* 100 MHz clock divided by 20 => 5 MHz */
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else if (rate == 25 * 1000 * 1000)
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return 0; /* 25 MHz clock divided by 4 => 6.25 MHz */
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else
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return 3; /* 40 MHz clock divided by 8 => 5 MHz */
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}
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static int ag71xx_mdio_reset(struct mii_bus *bus)
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{
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struct device_node *np = bus->dev.of_node;
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struct ag71xx *ag = bus->priv;
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struct device_node *np_ag = ag->pdev->dev.of_node;
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bool builtin_switch;
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u32 t;
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builtin_switch = of_property_read_bool(np, "builtin-switch");
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if (of_device_is_compatible(np_ag, "qca,ar7240-eth"))
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t = MII_CFG_CLK_DIV_6;
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else if (of_device_is_compatible(np_ag, "qca,ar9340-eth"))
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t = MII_CFG_CLK_DIV_58;
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else if (builtin_switch)
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t = MII_CFG_CLK_DIV_10;
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else
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t = MII_CFG_CLK_DIV_28;
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if (builtin_switch && of_device_is_compatible(np_ag, "qca,ar9340-eth")) {
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struct clk *ref_clk = of_clk_get(np, 0);
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int clock_rate;
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if (WARN_ON_ONCE(!ref_clk))
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clock_rate = 40 * 1000 * 1000;
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else
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clock_rate = clk_get_rate(ref_clk);
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t = ar934x_mdio_clock_div(clock_rate);
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clk_put(ref_clk);
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}
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
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udelay(100);
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regmap_write(ag->mii_regmap, AG71XX_REG_MII_CFG, t);
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udelay(100);
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return 0;
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}
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int ag71xx_mdio_init(struct ag71xx *ag)
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{
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struct device *parent = &ag->pdev->dev;
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struct device_node *np;
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struct mii_bus *mii_bus;
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bool builtin_switch;
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int i, err;
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np = of_get_child_by_name(parent->of_node, "mdio-bus");
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if (!np)
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return -ENODEV;
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if (!of_device_is_available(np)) {
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err = 0;
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goto err_out;
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}
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ag->mii_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
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if (!ag->mii_regmap)
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return -ENOENT;
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mii_bus = devm_mdiobus_alloc(parent);
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if (!mii_bus) {
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err = -ENOMEM;
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goto err_out;
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}
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ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio");
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builtin_switch = of_property_read_bool(np, "builtin-switch");
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mii_bus->name = "mdio";
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if (builtin_switch) {
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mii_bus->read = ar7240sw_phy_read;
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mii_bus->write = ar7240sw_phy_write;
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} else {
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mii_bus->read = ag71xx_mdio_mii_read;
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mii_bus->write = ag71xx_mdio_mii_write;
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}
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mii_bus->reset = ag71xx_mdio_reset;
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mii_bus->priv = ag;
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mii_bus->parent = parent;
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snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, bus_count++);
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if (!builtin_switch &&
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of_property_read_u32(np, "phy-mask", &mii_bus->phy_mask))
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mii_bus->phy_mask = 0;
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for (i = 0; i < PHY_MAX_ADDR; i++)
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mii_bus->irq[i] = PHY_POLL;
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if (!IS_ERR(ag->mdio_reset)) {
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reset_control_assert(ag->mdio_reset);
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msleep(100);
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reset_control_deassert(ag->mdio_reset);
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msleep(200);
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}
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err = of_mdiobus_register(mii_bus, np);
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if (err)
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goto err_out;
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ag->mii_bus = mii_bus;
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if (builtin_switch)
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ag71xx_ar7240_init(ag, np);
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return 0;
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err_out:
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of_node_put(np);
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return err;
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}
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void ag71xx_mdio_cleanup(struct ag71xx *ag)
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{
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if (!ag->mii_bus)
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return;
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ag71xx_ar7240_cleanup(ag);
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mdiobus_unregister(ag->mii_bus);
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}
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