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--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
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+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
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@@ -13,6 +13,7 @@ Required properties:
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* "allwinner,sun5i-a13-mmc"
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* "allwinner,sun7i-a20-mmc"
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* "allwinner,sun9i-a80-mmc"
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+ * "allwinner,sun50i-a64-emmc"
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* "allwinner,sun50i-a64-mmc"
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- reg : mmc controller base registers
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- clocks : a list with 4 phandle + clock specifier pairs
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--- a/drivers/mmc/host/sunxi-mmc.c
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+++ b/drivers/mmc/host/sunxi-mmc.c
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@@ -5,6 +5,7 @@
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* (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
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* (C) Copyright 2013-2014 David Lanzend<EFBFBD>rfer <david.lanzendoerfer@o2s.ch>
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* (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
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+ * (C) Copyright 2017 Sootech SA
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@@ -101,6 +102,7 @@
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(SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
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/* clock control bits */
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+#define SDXC_MASK_DATA0 BIT(31)
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#define SDXC_CARD_CLOCK_ON BIT(16)
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#define SDXC_LOW_POWER_ON BIT(17)
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@@ -253,6 +255,11 @@ struct sunxi_mmc_cfg {
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/* does the IP block support autocalibration? */
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bool can_calibrate;
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+
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+ /* Does DATA0 needs to be masked while the clock is updated */
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+ bool mask_data0;
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+
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+ bool needs_new_timings;
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};
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struct sunxi_mmc_host {
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@@ -482,7 +489,7 @@ static void sunxi_mmc_dump_errinfo(struc
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cmd->opcode == SD_IO_RW_DIRECT))
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return;
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- dev_err(mmc_dev(host->mmc),
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+ dev_dbg(mmc_dev(host->mmc),
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"smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
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host->mmc->index, cmd->opcode,
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data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
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@@ -654,11 +661,16 @@ static int sunxi_mmc_oclk_onoff(struct s
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unsigned long expire = jiffies + msecs_to_jiffies(750);
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u32 rval;
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+ dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
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+ oclk_en ? "en" : "dis");
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+
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rval = mmc_readl(host, REG_CLKCR);
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- rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
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+ rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
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if (oclk_en)
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rval |= SDXC_CARD_CLOCK_ON;
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+ if (host->cfg->mask_data0)
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+ rval |= SDXC_MASK_DATA0;
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mmc_writel(host, REG_CLKCR, rval);
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@@ -678,46 +690,29 @@ static int sunxi_mmc_oclk_onoff(struct s
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return -EIO;
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}
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+ if (host->cfg->mask_data0) {
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+ rval = mmc_readl(host, REG_CLKCR);
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+ mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
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+ }
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+
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return 0;
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}
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static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
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{
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- u32 reg = readl(host->reg_base + reg_off);
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- u32 delay;
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- unsigned long timeout;
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-
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if (!host->cfg->can_calibrate)
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return 0;
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- reg &= ~(SDXC_CAL_DL_MASK << SDXC_CAL_DL_SW_SHIFT);
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- reg &= ~SDXC_CAL_DL_SW_EN;
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-
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- writel(reg | SDXC_CAL_START, host->reg_base + reg_off);
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-
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- dev_dbg(mmc_dev(host->mmc), "calibration started\n");
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-
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- timeout = jiffies + HZ * SDXC_CAL_TIMEOUT;
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-
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- while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE)) {
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- if (time_before(jiffies, timeout))
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- cpu_relax();
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- else {
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- reg &= ~SDXC_CAL_START;
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- writel(reg, host->reg_base + reg_off);
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-
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- return -ETIMEDOUT;
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- }
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- }
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-
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- delay = (reg >> SDXC_CAL_DL_SHIFT) & SDXC_CAL_DL_MASK;
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-
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- reg &= ~SDXC_CAL_START;
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- reg |= (delay << SDXC_CAL_DL_SW_SHIFT) | SDXC_CAL_DL_SW_EN;
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-
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- writel(reg, host->reg_base + reg_off);
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-
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- dev_dbg(mmc_dev(host->mmc), "calibration ended, reg is 0x%x\n", reg);
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+ /*
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+ * FIXME:
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+ * This is not clear how the calibration is supposed to work
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+ * yet. The best rate have been obtained by simply setting the
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+ * delay to 0, as Allwinner does in its BSP.
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+ *
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+ * The only mode that doesn't have such a delay is HS400, that
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+ * is in itself a TODO.
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+ */
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+ writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
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return 0;
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}
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@@ -745,6 +740,7 @@ static int sunxi_mmc_clk_set_phase(struc
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index = SDXC_CLK_50M_DDR;
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}
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} else {
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+ dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
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return -EINVAL;
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}
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@@ -757,10 +753,21 @@ static int sunxi_mmc_clk_set_phase(struc
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static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
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struct mmc_ios *ios)
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{
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+ struct mmc_host *mmc = host->mmc;
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long rate;
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u32 rval, clock = ios->clock;
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int ret;
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+ ret = sunxi_mmc_oclk_onoff(host, 0);
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+ if (ret)
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+ return ret;
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+
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+ /* Our clock is gated now */
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+ mmc->actual_clock = 0;
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+
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+ if (!ios->clock)
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+ return 0;
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+
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/* 8 bit DDR requires a higher module clock */
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if (ios->timing == MMC_TIMING_MMC_DDR52 &&
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ios->bus_width == MMC_BUS_WIDTH_8)
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@@ -768,25 +775,21 @@ static int sunxi_mmc_clk_set_rate(struct
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rate = clk_round_rate(host->clk_mmc, clock);
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if (rate < 0) {
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- dev_err(mmc_dev(host->mmc), "error rounding clk to %d: %ld\n",
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+ dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
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clock, rate);
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return rate;
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}
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- dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %ld\n",
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+ dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
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clock, rate);
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/* setting clock rate */
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ret = clk_set_rate(host->clk_mmc, rate);
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if (ret) {
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- dev_err(mmc_dev(host->mmc), "error setting clk to %ld: %d\n",
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+ dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
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rate, ret);
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return ret;
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}
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- ret = sunxi_mmc_oclk_onoff(host, 0);
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- if (ret)
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- return ret;
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-
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/* clear internal divider */
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~0xff;
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@@ -798,6 +801,13 @@ static int sunxi_mmc_clk_set_rate(struct
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}
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mmc_writel(host, REG_CLKCR, rval);
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+ if (host->cfg->needs_new_timings) {
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+ /* Don't touch the delay bits */
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+ rval = mmc_readl(host, REG_SD_NTSR);
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+ rval |= SDXC_2X_TIMING_MODE;
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+ mmc_writel(host, REG_SD_NTSR, rval);
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+ }
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+
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ret = sunxi_mmc_clk_set_phase(host, ios, rate);
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if (ret)
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return ret;
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@@ -806,9 +816,22 @@ static int sunxi_mmc_clk_set_rate(struct
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if (ret)
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return ret;
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- /* TODO: enable calibrate on sdc2 SDXC_REG_DS_DL_REG of A64 */
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+ /*
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+ * FIXME:
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+ *
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+ * In HS400 we'll also need to calibrate the data strobe
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+ * signal. This should only happen on the MMC2 controller (at
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+ * least on the A64).
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+ */
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+
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+ ret = sunxi_mmc_oclk_onoff(host, 1);
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+ if (ret)
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+ return ret;
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- return sunxi_mmc_oclk_onoff(host, 1);
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+ /* And we just enabled our clock back */
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+ mmc->actual_clock = rate;
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+
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+ return 0;
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}
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static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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@@ -822,10 +845,13 @@ static void sunxi_mmc_set_ios(struct mmc
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break;
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case MMC_POWER_UP:
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- host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
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- ios->vdd);
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- if (host->ferror)
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- return;
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+ if (!IS_ERR(mmc->supply.vmmc)) {
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+ host->ferror = mmc_regulator_set_ocr(mmc,
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+ mmc->supply.vmmc,
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+ ios->vdd);
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+ if (host->ferror)
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+ return;
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+ }
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if (!IS_ERR(mmc->supply.vqmmc)) {
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host->ferror = regulator_enable(mmc->supply.vqmmc);
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@@ -847,7 +873,9 @@ static void sunxi_mmc_set_ios(struct mmc
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case MMC_POWER_OFF:
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dev_dbg(mmc_dev(mmc), "power off!\n");
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sunxi_mmc_reset_host(host);
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- mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
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+ if (!IS_ERR(mmc->supply.vmmc))
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+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
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+
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if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
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regulator_disable(mmc->supply.vqmmc);
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host->vqmmc_enabled = false;
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@@ -877,7 +905,7 @@ static void sunxi_mmc_set_ios(struct mmc
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mmc_writel(host, REG_GCTRL, rval);
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/* set up clock */
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- if (ios->clock && ios->power_mode) {
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+ if (ios->power_mode) {
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host->ferror = sunxi_mmc_clk_set_rate(host, ios);
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/* Android code had a usleep_range(50000, 55000); here */
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}
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@@ -1084,6 +1112,14 @@ static const struct sunxi_mmc_cfg sun50i
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.idma_des_size_bits = 16,
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.clk_delays = NULL,
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.can_calibrate = true,
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+ .mask_data0 = true,
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+ .needs_new_timings = true,
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+};
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+
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+static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
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+ .idma_des_size_bits = 13,
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+ .clk_delays = NULL,
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+ .can_calibrate = true,
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};
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static const struct of_device_id sunxi_mmc_of_match[] = {
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@@ -1092,6 +1128,7 @@ static const struct of_device_id sunxi_m
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{ .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
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{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
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{ .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
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+ { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
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