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400 lines
14 KiB
400 lines
14 KiB
From c58b398221d88ac0db29c3bb7522a4f48dfa102c Mon Sep 17 00:00:00 2001
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From: Yuan Yao <yao.yuan@freescale.com>
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Date: Tue, 17 Nov 2015 16:13:47 +0800
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Subject: [PATCH 087/113] mtd: spi-nor: fsl-quadspi: add big-endian support
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Add R/W functions for big- or little-endian registers:
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The qSPI controller's endian is independent of the CPU core's endian.
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So far, the qSPI have two versions for big-endian and little-endian.
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Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
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Acked-by: Han xu <han.xu@freescale.com>
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---
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drivers/mtd/spi-nor/fsl-quadspi.c | 157 +++++++++++++++++++++++--------------
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1 file changed, 97 insertions(+), 60 deletions(-)
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--- a/drivers/mtd/spi-nor/fsl-quadspi.c
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+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -275,6 +275,7 @@ struct fsl_qspi {
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u32 clk_rate;
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unsigned int chip_base_addr; /* We may support two chips. */
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bool has_second_chip;
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+ bool big_endian;
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struct mutex lock;
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struct pm_qos_request pm_qos_req;
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};
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@@ -300,6 +301,28 @@ static inline int needs_wakeup_wait_mode
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}
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/*
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+ * R/W functions for big- or little-endian registers:
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+ * The qSPI controller's endian is independent of the CPU core's endian.
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+ * So far, although the CPU core is little-endian but the qSPI have two
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+ * versions for big-endian and little-endian.
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+ */
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+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
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+{
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+ if (q->big_endian)
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+ iowrite32be(val, addr);
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+ else
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+ iowrite32(val, addr);
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+}
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+
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+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
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+{
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+ if (q->big_endian)
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+ return ioread32be(addr);
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+ else
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+ return ioread32(addr);
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+}
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+
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+/*
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* An IC bug makes us to re-arrange the 32-bit data.
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* The following chips, such as IMX6SLX, have fixed this bug.
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*/
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@@ -310,14 +333,14 @@ static inline u32 fsl_qspi_endian_xchg(s
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static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
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{
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- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
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- writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
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+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
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+ qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
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}
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static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
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{
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- writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
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- writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
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+ qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
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+ qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
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}
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static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
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@@ -326,8 +349,8 @@ static irqreturn_t fsl_qspi_irq_handler(
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u32 reg;
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/* clear interrupt */
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- reg = readl(q->iobase + QUADSPI_FR);
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- writel(reg, q->iobase + QUADSPI_FR);
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+ reg = qspi_readl(q, q->iobase + QUADSPI_FR);
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+ qspi_writel(q, reg, q->iobase + QUADSPI_FR);
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if (reg & QUADSPI_FR_TFF_MASK)
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complete(&q->c);
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@@ -348,7 +371,7 @@ static void fsl_qspi_init_lut(struct fsl
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/* Clear all the LUT table */
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for (i = 0; i < QUADSPI_LUT_NUM; i++)
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- writel(0, base + QUADSPI_LUT_BASE + i * 4);
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+ qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
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/* Quad Read */
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lut_base = SEQID_QUAD_READ * 4;
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@@ -364,14 +387,15 @@ static void fsl_qspi_init_lut(struct fsl
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dummy = 8;
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}
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- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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- writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
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+ qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
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base + QUADSPI_LUT(lut_base + 1));
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/* Write enable */
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lut_base = SEQID_WREN * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
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+ base + QUADSPI_LUT(lut_base));
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/* Page Program */
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lut_base = SEQID_PP * 4;
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@@ -385,13 +409,15 @@ static void fsl_qspi_init_lut(struct fsl
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addrlen = ADDR32BIT;
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}
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- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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- writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
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+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
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+ base + QUADSPI_LUT(lut_base + 1));
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/* Read Status */
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lut_base = SEQID_RDSR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1),
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
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+ LUT1(FSL_READ, PAD1, 0x1),
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base + QUADSPI_LUT(lut_base));
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/* Erase a sector */
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@@ -400,40 +426,46 @@ static void fsl_qspi_init_lut(struct fsl
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cmd = q->nor[0].erase_opcode;
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addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
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- writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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/* Erase the whole chip */
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lut_base = SEQID_CHIP_ERASE * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
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base + QUADSPI_LUT(lut_base));
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/* READ ID */
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lut_base = SEQID_RDID * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8),
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
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+ LUT1(FSL_READ, PAD1, 0x8),
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base + QUADSPI_LUT(lut_base));
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/* Write Register */
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lut_base = SEQID_WRSR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2),
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
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+ LUT1(FSL_WRITE, PAD1, 0x2),
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base + QUADSPI_LUT(lut_base));
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/* Read Configuration Register */
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lut_base = SEQID_RDCR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1),
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
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+ LUT1(FSL_READ, PAD1, 0x1),
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base + QUADSPI_LUT(lut_base));
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/* Write disable */
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lut_base = SEQID_WRDI * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
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+ base + QUADSPI_LUT(lut_base));
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/* Enter 4 Byte Mode (Micron) */
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lut_base = SEQID_EN4B * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
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+ base + QUADSPI_LUT(lut_base));
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/* Enter 4 Byte Mode (Spansion) */
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lut_base = SEQID_BRWR * 4;
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- writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
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+ base + QUADSPI_LUT(lut_base));
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fsl_qspi_lock_lut(q);
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}
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@@ -488,15 +520,16 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
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q->chip_base_addr, addr, len, cmd);
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/* save the reg */
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- reg = readl(base + QUADSPI_MCR);
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+ reg = qspi_readl(q, base + QUADSPI_MCR);
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- writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
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- writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
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+ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
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+ base + QUADSPI_SFAR);
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+ qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
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base + QUADSPI_RBCT);
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- writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
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+ qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
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do {
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- reg2 = readl(base + QUADSPI_SR);
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+ reg2 = qspi_readl(q, base + QUADSPI_SR);
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if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
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udelay(1);
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dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
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@@ -507,21 +540,22 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
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/* trigger the LUT now */
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seqid = fsl_qspi_get_seqid(q, cmd);
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- writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
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+ qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
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+ base + QUADSPI_IPCR);
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/* Wait for the interrupt. */
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if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
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dev_err(q->dev,
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"cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
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- cmd, addr, readl(base + QUADSPI_FR),
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- readl(base + QUADSPI_SR));
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+ cmd, addr, qspi_readl(q, base + QUADSPI_FR),
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+ qspi_readl(q, base + QUADSPI_SR));
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err = -ETIMEDOUT;
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} else {
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err = 0;
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}
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/* restore the MCR */
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- writel(reg, base + QUADSPI_MCR);
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+ qspi_writel(q, reg, base + QUADSPI_MCR);
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return err;
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}
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@@ -533,7 +567,7 @@ static void fsl_qspi_read_data(struct fs
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int i = 0;
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while (len > 0) {
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- tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
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+ tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
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tmp = fsl_qspi_endian_xchg(q, tmp);
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dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
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q->chip_base_addr, tmp);
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@@ -561,9 +595,9 @@ static inline void fsl_qspi_invalid(stru
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{
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u32 reg;
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- reg = readl(q->iobase + QUADSPI_MCR);
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+ reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
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reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
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- writel(reg, q->iobase + QUADSPI_MCR);
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+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
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/*
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* The minimum delay : 1 AHB + 2 SFCK clocks.
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@@ -572,7 +606,7 @@ static inline void fsl_qspi_invalid(stru
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udelay(1);
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reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
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- writel(reg, q->iobase + QUADSPI_MCR);
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+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
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}
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static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
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@@ -586,20 +620,20 @@ static int fsl_qspi_nor_write(struct fsl
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q->chip_base_addr, to, count);
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/* clear the TX FIFO. */
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- tmp = readl(q->iobase + QUADSPI_MCR);
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- writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
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+ tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
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+ qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
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/* fill the TX data to the FIFO */
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for (j = 0, i = ((count + 3) / 4); j < i; j++) {
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tmp = fsl_qspi_endian_xchg(q, *txbuf);
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- writel(tmp, q->iobase + QUADSPI_TBDR);
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+ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
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txbuf++;
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}
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/* fill the TXFIFO upto 16 bytes for i.MX7d */
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if (needs_fill_txfifo(q))
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for (; i < 4; i++)
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- writel(tmp, q->iobase + QUADSPI_TBDR);
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+ qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
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/* Trigger it */
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ret = fsl_qspi_runcmd(q, opcode, to, count);
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@@ -615,10 +649,10 @@ static void fsl_qspi_set_map_addr(struct
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int nor_size = q->nor_size;
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void __iomem *base = q->iobase;
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- writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
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- writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
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- writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
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- writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
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+ qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
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+ qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
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+ qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
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+ qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
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}
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/*
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@@ -640,24 +674,26 @@ static void fsl_qspi_init_abh_read(struc
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int seqid;
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/* AHB configuration for access buffer 0/1/2 .*/
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- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
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- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
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- writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
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+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
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+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
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+ qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
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/*
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* Set ADATSZ with the maximum AHB buffer size to improve the
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* read performance.
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*/
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- writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
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- << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
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+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
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+ ((q->devtype_data->ahb_buf_size / 8)
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+ << QUADSPI_BUF3CR_ADATSZ_SHIFT),
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+ base + QUADSPI_BUF3CR);
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/* We only use the buffer3 */
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- writel(0, base + QUADSPI_BUF0IND);
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- writel(0, base + QUADSPI_BUF1IND);
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- writel(0, base + QUADSPI_BUF2IND);
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+ qspi_writel(q, 0, base + QUADSPI_BUF0IND);
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+ qspi_writel(q, 0, base + QUADSPI_BUF1IND);
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+ qspi_writel(q, 0, base + QUADSPI_BUF2IND);
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/* Set the default lut sequence for AHB Read. */
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seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
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- writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
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+ qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
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q->iobase + QUADSPI_BFGENCR);
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}
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@@ -713,7 +749,7 @@ static int fsl_qspi_nor_setup(struct fsl
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return ret;
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/* Reset the module */
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- writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
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+ qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
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base + QUADSPI_MCR);
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udelay(1);
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@@ -721,24 +757,24 @@ static int fsl_qspi_nor_setup(struct fsl
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fsl_qspi_init_lut(q);
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/* Disable the module */
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- writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
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+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
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base + QUADSPI_MCR);
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|
|
|
- reg = readl(base + QUADSPI_SMPR);
|
|
- writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
|
|
+ reg = qspi_readl(q, base + QUADSPI_SMPR);
|
|
+ qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
|
|
| QUADSPI_SMPR_FSPHS_MASK
|
|
| QUADSPI_SMPR_HSENA_MASK
|
|
| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
|
|
|
|
/* Enable the module */
|
|
- writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
|
|
+ qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
|
|
base + QUADSPI_MCR);
|
|
|
|
/* clear all interrupt status */
|
|
- writel(0xffffffff, q->iobase + QUADSPI_FR);
|
|
+ qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);
|
|
|
|
/* enable the interrupt */
|
|
- writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
|
|
+ qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
|
|
|
|
return 0;
|
|
}
|
|
@@ -954,6 +990,7 @@ static int fsl_qspi_probe(struct platfor
|
|
if (IS_ERR(q->iobase))
|
|
return PTR_ERR(q->iobase);
|
|
|
|
+ q->big_endian = of_property_read_bool(np, "big-endian");
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
"QuadSPI-memory");
|
|
if (!devm_request_mem_region(dev, res->start, resource_size(res),
|
|
@@ -1101,8 +1138,8 @@ static int fsl_qspi_remove(struct platfo
|
|
}
|
|
|
|
/* disable the hardware */
|
|
- writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
|
|
- writel(0x0, q->iobase + QUADSPI_RSER);
|
|
+ qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
|
|
+ qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
|
|
|
|
mutex_destroy(&q->lock);
|
|
|
|
|