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122 lines
3.5 KiB
122 lines
3.5 KiB
From acfc6e9b34b3b3ca0d8bbe366dd08b0fac21c740 Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <yunhui.cui@nxp.com>
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Date: Tue, 2 Feb 2016 12:21:12 +0800
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Subject: [PATCH 101/113] mtd: spi-nor: fsl-quadspi: extend support for some
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special requerment.
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Add extra info in LUT table to support some special requerments.
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Spansion S25FS-S family flash need some special operations.
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Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
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---
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drivers/mtd/spi-nor/fsl-quadspi.c | 44 +++++++++++++++++++++++++++++++++++--
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include/linux/mtd/spi-nor.h | 4 ++++
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2 files changed, 46 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/spi-nor/fsl-quadspi.c
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+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -205,6 +205,9 @@
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#define SEQID_RDCR 9
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#define SEQID_EN4B 10
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#define SEQID_BRWR 11
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+#define SEQID_RDAR 12
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+#define SEQID_WRAR 13
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+
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#define QUADSPI_MIN_IOMAP SZ_4M
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@@ -470,6 +473,28 @@ static void fsl_qspi_init_lut(struct fsl
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qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
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base + QUADSPI_LUT(lut_base));
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+ /*
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+ * Read any device register.
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+ * Used for Spansion S25FS-S family flash only.
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+ */
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+ lut_base = SEQID_RDAR * 4;
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
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+ LUT1(ADDR, PAD1, ADDR24BIT),
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+ base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
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+ base + QUADSPI_LUT(lut_base + 1));
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+
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+ /*
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+ * Write any device register.
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+ * Used for Spansion S25FS-S family flash only.
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+ */
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+ lut_base = SEQID_WRAR * 4;
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
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+ LUT1(ADDR, PAD1, ADDR24BIT),
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+ base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
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+ base + QUADSPI_LUT(lut_base + 1));
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+
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fsl_qspi_lock_lut(q);
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}
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@@ -477,9 +502,15 @@ static void fsl_qspi_init_lut(struct fsl
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static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
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{
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switch (cmd) {
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+ case SPINOR_OP_READ4_1_1_4:
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case SPINOR_OP_READ_1_1_4:
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case SPINOR_OP_READ_FAST:
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+ case SPINOR_OP_READ4_FAST:
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return SEQID_READ;
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+ case SPINOR_OP_SPANSION_RDAR:
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+ return SEQID_RDAR;
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+ case SPINOR_OP_SPANSION_WRAR:
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+ return SEQID_WRAR;
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case SPINOR_OP_WREN:
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return SEQID_WREN;
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case SPINOR_OP_WRDI:
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@@ -491,6 +522,7 @@ static int fsl_qspi_get_seqid(struct fsl
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case SPINOR_OP_CHIP_ERASE:
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return SEQID_CHIP_ERASE;
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case SPINOR_OP_PP:
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+ case SPINOR_OP_PP_4B:
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return SEQID_PP;
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case SPINOR_OP_RDID:
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return SEQID_RDID;
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@@ -830,8 +862,12 @@ static int fsl_qspi_read_reg(struct spi_
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{
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int ret;
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struct fsl_qspi *q = nor->priv;
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+ u32 to = 0;
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+
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+ if (opcode == SPINOR_OP_SPANSION_RDAR)
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+ memcpy(&to, nor->cmd_buf, 4);
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- ret = fsl_qspi_runcmd(q, opcode, 0, len);
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+ ret = fsl_qspi_runcmd(q, opcode, to, len);
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if (ret)
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return ret;
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@@ -843,9 +879,13 @@ static int fsl_qspi_write_reg(struct spi
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{
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struct fsl_qspi *q = nor->priv;
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int ret;
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+ u32 to = 0;
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+
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+ if (opcode == SPINOR_OP_SPANSION_WRAR)
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+ memcpy(&to, nor->cmd_buf, 4);
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if (!buf) {
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- ret = fsl_qspi_runcmd(q, opcode, 0, 1);
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+ ret = fsl_qspi_runcmd(q, opcode, to, 1);
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if (ret)
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return ret;
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -74,6 +74,10 @@
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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+/* Used for Spansion S25FS-S family flash only. */
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+#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
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+#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
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+
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/* Used for Micron flashes only. */
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#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
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#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
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