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211 lines
8.0 KiB
211 lines
8.0 KiB
From 70f970222bc1096689ae1bffeb9ed09a7c4bed07 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sat, 12 Nov 2011 12:19:55 +0100
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Subject: [PATCH 28/60] MIPS: BCM63XX: add HSSPI register definitions
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 47 +++++++++++++++++++++
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2 files changed, 65 insertions(+), 0 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -116,6 +116,7 @@ enum bcm63xx_regs_set {
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RSET_UART1,
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RSET_GPIO,
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RSET_SPI,
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+ RSET_HSSPI,
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RSET_UDC0,
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RSET_OHCI0,
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RSET_OHCI_PRIV,
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@@ -161,6 +162,7 @@ enum bcm63xx_regs_set {
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#define RSET_ENETDMA_SIZE 2048
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#define RSET_ENETSW_SIZE 65536
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#define RSET_UART_SIZE 24
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+#define RSET_HSSPI_SIZE 1536
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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#define RSET_EHCI_SIZE 256
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@@ -186,6 +188,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_UART1_BASE (0xb0000120)
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#define BCM_6328_GPIO_BASE (0xb0000080)
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#define BCM_6328_SPI_BASE (0xdeadbeef)
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+#define BCM_6328_HSSPI_BASE (0xb0001000)
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#define BCM_6328_UDC0_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xb000c000)
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#define BCM_6328_OHCI0_BASE (0xb0002600)
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@@ -232,6 +235,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UART1_BASE (0xdeadbeef)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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+#define BCM_6338_HSSPI_BASE (0xdeadbeef)
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#define BCM_6338_UDC0_BASE (0xdeadbeef)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_OHCI0_BASE (0xdeadbeef)
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@@ -279,6 +283,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_UART1_BASE (0xdeadbeef)
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#define BCM_6345_GPIO_BASE (0xfffe0400)
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#define BCM_6345_SPI_BASE (0xdeadbeef)
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+#define BCM_6345_HSSPI_BASE (0xdeadbeef)
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#define BCM_6345_UDC0_BASE (0xdeadbeef)
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#define BCM_6345_USBDMA_BASE (0xfffe2800)
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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@@ -325,6 +330,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_UART1_BASE (0xdeadbeef)
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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+#define BCM_6348_HSSPI_BASE (0xdeadbeef)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_USBDMA_BASE (0xdeadbeef)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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@@ -370,6 +376,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_UART1_BASE (0xfffe0120)
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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#define BCM_6358_SPI_BASE (0xfffe0800)
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+#define BCM_6358_HSSPI_BASE (0xdeadbeef)
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#define BCM_6358_UDC0_BASE (0xfffe0800)
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#define BCM_6358_USBDMA_BASE (0xdeadbeef)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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@@ -416,6 +423,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_UART1_BASE (0xb0000120)
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#define BCM_6368_GPIO_BASE (0xb0000080)
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#define BCM_6368_SPI_BASE (0xb0000800)
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+#define BCM_6368_HSSPI_BASE (0xdeadbeef)
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#define BCM_6368_UDC0_BASE (0xdeadbeef)
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#define BCM_6368_USBDMA_BASE (0xb0004800)
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#define BCM_6368_OHCI0_BASE (0xb0001600)
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@@ -467,6 +475,7 @@ extern const unsigned long *bcm63xx_regs
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__GEN_RSET_BASE(__cpu, UART1) \
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__GEN_RSET_BASE(__cpu, GPIO) \
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__GEN_RSET_BASE(__cpu, SPI) \
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+ __GEN_RSET_BASE(__cpu, HSSPI) \
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__GEN_RSET_BASE(__cpu, UDC0) \
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__GEN_RSET_BASE(__cpu, OHCI0) \
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__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
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@@ -510,6 +519,7 @@ extern const unsigned long *bcm63xx_regs
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[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
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[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
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[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
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+ [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
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[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
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[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
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[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
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@@ -584,6 +594,7 @@ enum bcm63xx_irq {
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IRQ_ENET0,
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IRQ_ENET1,
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IRQ_ENET_PHY,
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+ IRQ_HSSPI,
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IRQ_OHCI0,
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IRQ_EHCI0,
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IRQ_USBD,
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@@ -626,6 +637,7 @@ enum bcm63xx_irq {
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#define BCM_6328_ENET0_IRQ 0
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#define BCM_6328_ENET1_IRQ 0
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#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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+#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
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#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
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#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
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#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
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@@ -671,6 +683,7 @@ enum bcm63xx_irq {
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#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6338_ENET1_IRQ 0
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#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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+#define BCM_6338_HSSPI_IRQ 0
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#define BCM_6338_OHCI0_IRQ 0
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#define BCM_6338_EHCI0_IRQ 0
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#define BCM_6338_USBD_IRQ 0
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@@ -709,6 +722,7 @@ enum bcm63xx_irq {
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#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6345_ENET1_IRQ 0
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#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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+#define BCM_6345_HSSPI_IRQ 0
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#define BCM_6345_OHCI0_IRQ 0
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#define BCM_6345_EHCI0_IRQ 0
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#define BCM_6345_USBD_IRQ 0
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@@ -747,6 +761,7 @@ enum bcm63xx_irq {
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#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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+#define BCM_6348_HSSPI_IRQ 0
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#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6348_EHCI0_IRQ 0
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#define BCM_6348_USBD_IRQ 0
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@@ -785,6 +800,7 @@ enum bcm63xx_irq {
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#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
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#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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+#define BCM_6358_HSSPI_IRQ 0
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#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6358_USBD_IRQ 0
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@@ -832,6 +848,7 @@ enum bcm63xx_irq {
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#define BCM_6368_ENET0_IRQ 0
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#define BCM_6368_ENET1_IRQ 0
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#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
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+#define BCM_6368_HSSPI_IRQ 0
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#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
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@@ -879,6 +896,7 @@ extern const int *bcm63xx_irqs;
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[IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
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[IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
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[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
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+ [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
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[IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
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[IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
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[IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1404,4 +1404,51 @@
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#define PCIE_DEVICE_OFFSET 0x8000
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+/*************************************************************************
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+ * _REG relative to RSET_HSSPI
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+ *************************************************************************/
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+
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+#define HSSPI_GLOBAL_CTRL_REG 0x0
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+#define GLOBAL_CTRL_CLK_POLARITY (1 << 17)
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+#define GLOBAL_CTRL_CLK_GATE_SSOFF (1 << 16)
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+
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+#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
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+
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+#define HSSPI_INT_STATUS_REG 0x8
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+#define HSSPI_INT_STATUS_MASKED_REG 0xc
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+#define HSSPI_INT_MASK_REG 0x10
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+
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+#define HSSPI_PING0_CMD_DONE (1 << 0)
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+
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+#define HSSPI_INT_CLEAR_ALL 0xff001f1f
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+
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+#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
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+#define PINGPONG_CMD_COMMAND_MASK 0xf
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+#define PINGPONG_COMMAND_NOOP 0
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+#define PINGPONG_COMMAND_START_NOW 1
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+#define PINGPONG_COMMAND_START_TRIGGER 2
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+#define PINGPONG_COMMAND_HALT 3
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+#define PINGPONG_COMMAND_FLUSH 4
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+#define PINGPONG_CMD_PROFILE_SHIFT 8
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+#define PINGPONG_CMD_SS_SHIFT 12
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+
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+#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
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+
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+#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
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+#define CLK_CTRL_ACCUM_RST_ON_LOOP (1 << 15)
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+
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+#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
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+#define SIGNAL_CTRL_LATCH_RISING (1 << 12)
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+#define SIGNAL_CTRL_LAUNCH_RISING (1 << 13)
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+#define SIGNAL_CTRL_ASYNC_INPUT_PATH (1 << 16)
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+
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+#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
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+#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
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+#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
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+#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
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+#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
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+#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
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+
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+#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
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+
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#endif /* BCM63XX_REGS_H_ */
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