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239 lines
7.1 KiB
239 lines
7.1 KiB
From 5f33206ebe4fb4a2cc8634f29c3e3c9bc01e3416 Mon Sep 17 00:00:00 2001
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From: Eddie Huang <eddie.huang@mediatek.com>
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Date: Wed, 6 May 2015 16:37:07 +0800
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Subject: [PATCH 31/76] I2C: mediatek: Add driver for MediaTek MT8173 I2C
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controller
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Add mediatek MT8173 I2C controller driver. Compare to I2C controller
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of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
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also increase message size to 64kb.
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Signed-off-by: Xudong Chen <xudong.chen@mediatek.com>
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Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
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Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
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---
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drivers/i2c/busses/i2c-mt65xx.c | 104 ++++++++++++++++++++++++++++-----------
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1 file changed, 76 insertions(+), 28 deletions(-)
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--- a/drivers/i2c/busses/i2c-mt65xx.c
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+++ b/drivers/i2c/busses/i2c-mt65xx.c
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@@ -33,10 +33,13 @@
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#include <linux/clk.h>
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#include <linux/completion.h>
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+#define I2C_RS_TRANSFER (1 << 4)
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#define I2C_HS_NACKERR (1 << 2)
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#define I2C_ACKERR (1 << 1)
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#define I2C_TRANSAC_COMP (1 << 0)
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#define I2C_TRANSAC_START (1 << 0)
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+#define I2C_RS_MUL_CNFG (1 << 15)
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+#define I2C_RS_MUL_TRIG (1 << 14)
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#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0)
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#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0)
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#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8)
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@@ -67,6 +70,9 @@
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#define MAX_MSG_NUM_MT6577 1
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#define MAX_DMA_TRANS_SIZE_MT6577 255
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#define MAX_WRRD_TRANS_SIZE_MT6577 31
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+#define MAX_MSG_NUM_MT8173 65535
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+#define MAX_DMA_TRANS_SIZE_MT8173 65535
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+#define MAX_WRRD_TRANS_SIZE_MT8173 65535
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#define MAX_SAMPLE_CNT_DIV 8
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#define MAX_STEP_CNT_DIV 64
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#define MAX_HS_STEP_CNT_DIV 8
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@@ -139,6 +145,7 @@ struct mtk_i2c_compatible {
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const struct i2c_adapter_quirks *quirks;
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unsigned char pmic_i2c;
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unsigned char dcm;
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+ unsigned char auto_restart;
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};
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struct mtk_i2c {
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@@ -172,21 +179,39 @@ static const struct i2c_adapter_quirks m
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.max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577,
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};
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+static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
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+ .max_num_msgs = MAX_MSG_NUM_MT8173,
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+ .max_write_len = MAX_DMA_TRANS_SIZE_MT8173,
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+ .max_read_len = MAX_DMA_TRANS_SIZE_MT8173,
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+ .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT8173,
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+ .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT8173,
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+};
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+
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static const struct mtk_i2c_compatible mt6577_compat = {
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.quirks = &mt6577_i2c_quirks,
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.pmic_i2c = 0,
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.dcm = 1,
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+ .auto_restart = 0,
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};
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static const struct mtk_i2c_compatible mt6589_compat = {
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.quirks = &mt6577_i2c_quirks,
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.pmic_i2c = 1,
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.dcm = 0,
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+ .auto_restart = 0,
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+};
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+
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+static const struct mtk_i2c_compatible mt8173_compat = {
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+ .quirks = &mt8173_i2c_quirks,
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+ .pmic_i2c = 0,
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+ .dcm = 1,
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+ .auto_restart = 1,
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};
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static const struct of_device_id mtk_i2c_of_match[] = {
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{ .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
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{ .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
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+ { .compatible = "mediatek,mt8173-i2c", .data = (void *)&mt8173_compat },
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{}
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};
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MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
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@@ -343,9 +368,11 @@ static int mtk_i2c_set_speed(struct mtk_
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return 0;
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}
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-static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
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+static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
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+ int num, int left_num)
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{
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u16 addr_reg;
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+ u16 start_reg;
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u16 control_reg;
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dma_addr_t rpaddr = 0;
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dma_addr_t wpaddr = 0;
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@@ -361,6 +388,8 @@ static int mtk_i2c_do_transfer(struct mt
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control_reg |= I2C_CONTROL_RS;
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if (i2c->op == I2C_MASTER_WRRD)
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control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
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+ if (left_num >= 1)
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+ control_reg |= I2C_CONTROL_RS;
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mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
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/* set start condition */
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@@ -375,13 +404,13 @@ static int mtk_i2c_do_transfer(struct mt
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mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
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/* Clear interrupt status */
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- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
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- i2c, OFFSET_INTR_STAT);
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+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
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+ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
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mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
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/* Enable interrupt */
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- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
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- i2c, OFFSET_INTR_MASK);
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+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
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+ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_MASK);
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/* Set transfer and transaction len */
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if (i2c->op == I2C_MASTER_WRRD) {
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@@ -390,7 +419,7 @@ static int mtk_i2c_do_transfer(struct mt
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mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
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} else {
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mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN);
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- mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
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+ mtk_i2c_writew(num, i2c, OFFSET_TRANSAC_LEN);
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}
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/* Prepare buffer data to start transfer */
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@@ -436,13 +465,23 @@ static int mtk_i2c_do_transfer(struct mt
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/* flush before sending start */
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mb();
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mtk_i2c_writel_dma(I2C_DMA_START_EN, i2c, OFFSET_EN);
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- mtk_i2c_writew(I2C_TRANSAC_START, i2c, OFFSET_START);
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+
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+ if (!i2c->dev_comp->auto_restart) {
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+ start_reg = I2C_TRANSAC_START;
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+ } else {
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+ if (left_num >= 1)
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+ start_reg = I2C_TRANSAC_START | I2C_RS_MUL_CNFG
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+ | I2C_RS_MUL_TRIG;
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+ else
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+ start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
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+ }
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+ mtk_i2c_writew(start_reg, i2c, OFFSET_START);
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ret = wait_for_completion_timeout(&i2c->msg_complete,
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i2c->adap.timeout);
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/* Clear interrupt mask */
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- mtk_i2c_writew(~(I2C_HS_NACKERR | I2C_ACKERR
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+ mtk_i2c_writew(~(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
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| I2C_TRANSAC_COMP), i2c, OFFSET_INTR_MASK);
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if (i2c->op == I2C_MASTER_WR) {
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@@ -472,6 +511,10 @@ static int mtk_i2c_do_transfer(struct mt
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return -EREMOTEIO;
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}
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+ if (i2c->irq_stat & I2C_RS_TRANSFER)
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+ dev_dbg(i2c->dev, "addr: %x, restart transfer interrupt.\n",
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+ msgs->addr);
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+
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return 0;
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}
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@@ -486,28 +529,33 @@ static int mtk_i2c_transfer(struct i2c_a
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if (ret)
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return ret;
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- if (msgs->buf == NULL) {
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- dev_dbg(i2c->dev, "data buffer is NULL.\n");
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- ret = -EINVAL;
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- goto err_exit;
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- }
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-
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- if (msgs->flags & I2C_M_RD)
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- i2c->op = I2C_MASTER_RD;
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- else
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- i2c->op = I2C_MASTER_WR;
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+ while (left_num--) {
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+ if (msgs->buf == NULL) {
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+ dev_dbg(i2c->dev, "data buffer is NULL.\n");
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+ ret = -EINVAL;
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+ goto err_exit;
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+ }
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- if (num > 1) {
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- /* combined two messages into one transaction */
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- i2c->op = I2C_MASTER_WRRD;
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- left_num--;
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- }
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+ if (msgs->flags & I2C_M_RD)
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+ i2c->op = I2C_MASTER_RD;
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+ else
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+ i2c->op = I2C_MASTER_WR;
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+
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+ if (!i2c->dev_comp->auto_restart) {
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+ if (num > 1) {
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+ /* combined two messages into one transaction */
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+ i2c->op = I2C_MASTER_WRRD;
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+ left_num--;
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+ }
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+ }
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- /* always use DMA mode. */
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- ret = mtk_i2c_do_transfer(i2c, msgs);
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- if (ret < 0)
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- goto err_exit;
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+ /* always use DMA mode. */
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+ ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
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+ if (ret < 0)
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+ goto err_exit;
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+ msgs++;
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+ }
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/* the return value is number of executed messages */
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ret = num;
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@@ -521,7 +569,7 @@ static irqreturn_t mtk_i2c_irq(int irqno
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struct mtk_i2c *i2c = dev_id;
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i2c->irq_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
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- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR
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+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
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| I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
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complete(&i2c->msg_complete);
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