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25 lines
1.4 KiB
25 lines
1.4 KiB
From 9b3d423707c3b1f6633be1be7e959623e10c596b Mon Sep 17 00:00:00 2001
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From: Jiada Wang <jiada_wang@mentor.com>
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Date: Wed, 30 Oct 2013 04:25:51 -0700
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Subject: [PATCH] ARM: i.MX6q: fix the wrong parent of can_root clock
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instead of pll3_usb_otg the parent of can_root clock
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should be pll3_60m.
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Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/mach-imx/clk-imx6q.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -442,7 +442,7 @@ int __init mx6q_clocks_init(void)
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clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
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clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
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clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
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- clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
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+ clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
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clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
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clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
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clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
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