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125 lines
3.8 KiB
125 lines
3.8 KiB
From c7045330c5976eb31bd79bc57c5db684588d595e Mon Sep 17 00:00:00 2001
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From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
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Date: Mon, 7 Oct 2013 10:44:55 +0300
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Subject: [PATCH 158/182] usb: dwc3: qcom: Add device tree binding
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QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
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(SNPS) and HS, SS PHY's control and configuration registers.
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It could operate in device mode (SS, HS, FS) and host
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mode (SS, HS, FS, LS).
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Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
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Acked-by: Stephen Warren <swarren@nvidia.com>
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---
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.../devicetree/bindings/usb/qcom,dwc3.txt | 104 ++++++++++++++++++++
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1 file changed, 104 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
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@@ -0,0 +1,104 @@
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+Qualcomm SuperSpeed DWC3 USB SoC controller
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+
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+
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+QCOM DWC3 Highspeed USB PHY
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+========================
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+Required properities:
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+- compatible: should contain "qcom,dwc3-hsphy";
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+- reg: offset and length of the register set in the memory map
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+- clocks: A list of phandle + clock-specifier pairs for the
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+ clocks listed in clock-names
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+- clock-names: Should contain the following:
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+ "utmi" UTMI clock
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+- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY.
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+- v3p3-supply: phandle to the regulator for the 3.3v supply to HSPHY.
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+- vbus-supply: phandle to the regulator for the vbus supply for host
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+ mode.
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+- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY
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+ digital circuit operation.
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+
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+Optional clocks:
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+ "xo" External reference clock
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+
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+
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+QCOM DWC3 Superspeed USB PHY
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+=========================
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+Required properities:
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+- compatible: should contain "qcom,dwc3-ssphy";
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+- reg: offset and length of the register set in the memory map
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+- clocks: A list of phandle + clock-specifier pairs for the
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+ clocks listed in clock-names
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+- clock-names: Should contain the following:
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+ "ref" Reference clock used in host mode.
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+- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY.
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+- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY
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+ digital circuit operation.
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+
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+Optional clocks:
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+ "xo" External reference clock
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+
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+QCOM DWC3 controller wrapper
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+===========================
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+Required properties:
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+- compatible: should contain "qcom,dwc3"
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+- clocks: A list of phandle + clock-specifier pairs for the
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+ clocks listed in clock-names
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+- clock-names: Should contain the following:
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+ "core" Master/Core clock, have to be >= 125 MHz for SS
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+ operation and >= 60MHz for HS operation
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+
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+Optional clocks:
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+ "iface" System bus AXI clock. Not present on all platforms
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+ "sleep" Sleep clock, used when USB3 core goes into low
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+ power mode (U3).
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+
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+Optional regulator:
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+- gdsc-supply: phandle to the regulator from globally distributed
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+ switch controller
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+
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+Required child node:
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+A child node must exist to represent the core DWC3 IP block. The name of
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+the node is not important. The content of the node is defined in dwc3.txt.
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+
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+Example device nodes:
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+
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+ hs_phy_0: phy@110f8800 {
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+ compatible = "qcom,dwc3-hsphy";
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+ reg = <0x110f8800 0x30>;
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+ clocks = <&gcc USB30_0_UTMI_CLK>;
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+ clock-names = "utmi";
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+
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+ status = "disabled";
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+ };
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+
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+ ss_phy_0: phy@110f8830 {
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+ compatible = "qcom,dwc3-ssphy";
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+ reg = <0x110f8830 0x30>;
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+
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+ clocks = <&gcc USB30_0_MASTER_CLK>;
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+ clock-names = "ref";
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+
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+ status = "disabled";
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+ };
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+
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+ usb3_0: usb30@0 {
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+ compatible = "qcom,dwc3";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc USB30_0_MASTER_CLK>;
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+ clock-names = "core";
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+
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+ ranges;
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+
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+ status = "disabled";
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+
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+ dwc3@11000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x11000000 0xcd00>;
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+ interrupts = <0 110 0x4>;
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+ usb-phy = <&hs_phy_0>, <&ss_phy_0>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ tx-fifo-resize;
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+ dr_mode = "host";
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+ };
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+ };
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