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392 lines
13 KiB
392 lines
13 KiB
From d9d0181f74146507026c31cccd52dda27ec3d966 Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Wed, 17 Jan 2018 14:57:31 +0800
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Subject: [PATCH 06/30] mtd: support layerscape
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This is an integrated patch for layerscape ifc-nor-nand support.
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Signed-off-by: Alison Wang <b18965@freescale.com>
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Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/memory/Kconfig | 2 +-
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drivers/memory/fsl_ifc.c | 263 ++++++++++++++++++++++++++++++++++++++++
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drivers/mtd/maps/physmap_of.c | 4 +
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drivers/mtd/nand/Kconfig | 2 +-
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drivers/mtd/nand/fsl_ifc_nand.c | 5 +-
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include/linux/fsl_ifc.h | 7 ++
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6 files changed, 280 insertions(+), 3 deletions(-)
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--- a/drivers/memory/Kconfig
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+++ b/drivers/memory/Kconfig
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@@ -115,7 +115,7 @@ config FSL_CORENET_CF
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config FSL_IFC
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bool
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- depends on FSL_SOC || ARCH_LAYERSCAPE
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+ depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
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config JZ4780_NEMC
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bool "Ingenic JZ4780 SoC NEMC driver"
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--- a/drivers/memory/fsl_ifc.c
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+++ b/drivers/memory/fsl_ifc.c
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@@ -24,6 +24,7 @@
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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+#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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@@ -37,6 +38,8 @@
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struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
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EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
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+#define FSL_IFC_V1_3_0 0x01030000
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+#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
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/*
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* convert_ifc_address - convert the base address
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@@ -311,6 +314,261 @@ err:
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return ret;
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}
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+#ifdef CONFIG_PM_SLEEP
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+/* save ifc registers */
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+static int fsl_ifc_suspend(struct device *dev)
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+{
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+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
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+ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
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+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
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+ __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
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+ gpcm_evter_intr_en;
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+ uint32_t ifc_bank, i;
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+
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+ ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
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+ if (!ctrl->saved_gregs)
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+ return -ENOMEM;
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+ ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
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+ if (!ctrl->saved_rregs)
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+ return -ENOMEM;
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+
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+ cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
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+ nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
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+ nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
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+ gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
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+
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+/* IFC interrupts disabled */
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+
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+ ifc_out32(0x0, &fcm->cm_evter_intr_en);
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+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
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+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
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+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
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+
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+ if (ctrl->saved_gregs) {
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+ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
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+ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
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+ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
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+ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
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+ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
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+ ctrl->saved_gregs->amask_cs[ifc_bank].amask =
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+ ifc_in32(&fcm->amask_cs[ifc_bank].amask);
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+ ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
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+ ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
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+ ctrl->saved_gregs->csor_cs[ifc_bank].csor =
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+ ifc_in32(&fcm->csor_cs[ifc_bank].csor);
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+ for (i = 0; i < 4; i++) {
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+ ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
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+ ifc_in32(
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+ &fcm->ftim_cs[ifc_bank].ftim[i]);
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+ }
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+ }
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+
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+ ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
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+ ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
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+ ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
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+ ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
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+ ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
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+ }
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+
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+ if (ctrl->saved_rregs) {
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+ /* IFC controller NAND machine registers */
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+ ctrl->saved_rregs->ifc_nand.ncfgr =
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+ ifc_in32(&runtime->ifc_nand.ncfgr);
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+ ctrl->saved_rregs->ifc_nand.nand_fcr0 =
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+ ifc_in32(&runtime->ifc_nand.nand_fcr0);
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+ ctrl->saved_rregs->ifc_nand.nand_fcr1 =
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+ ifc_in32(&runtime->ifc_nand.nand_fcr1);
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+ ctrl->saved_rregs->ifc_nand.row0 =
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+ ifc_in32(&runtime->ifc_nand.row0);
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+ ctrl->saved_rregs->ifc_nand.row1 =
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+ ifc_in32(&runtime->ifc_nand.row1);
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+ ctrl->saved_rregs->ifc_nand.col0 =
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+ ifc_in32(&runtime->ifc_nand.col0);
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+ ctrl->saved_rregs->ifc_nand.col1 =
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+ ifc_in32(&runtime->ifc_nand.col1);
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+ ctrl->saved_rregs->ifc_nand.row2 =
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+ ifc_in32(&runtime->ifc_nand.row2);
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+ ctrl->saved_rregs->ifc_nand.col2 =
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+ ifc_in32(&runtime->ifc_nand.col2);
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+ ctrl->saved_rregs->ifc_nand.row3 =
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+ ifc_in32(&runtime->ifc_nand.row3);
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+ ctrl->saved_rregs->ifc_nand.col3 =
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+ ifc_in32(&runtime->ifc_nand.col3);
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+
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+ ctrl->saved_rregs->ifc_nand.nand_fbcr =
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+ ifc_in32(&runtime->ifc_nand.nand_fbcr);
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+ ctrl->saved_rregs->ifc_nand.nand_fir0 =
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+ ifc_in32(&runtime->ifc_nand.nand_fir0);
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+ ctrl->saved_rregs->ifc_nand.nand_fir1 =
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+ ifc_in32(&runtime->ifc_nand.nand_fir1);
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+ ctrl->saved_rregs->ifc_nand.nand_fir2 =
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+ ifc_in32(&runtime->ifc_nand.nand_fir2);
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+ ctrl->saved_rregs->ifc_nand.nand_csel =
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+ ifc_in32(&runtime->ifc_nand.nand_csel);
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+ ctrl->saved_rregs->ifc_nand.nandseq_strt =
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+ ifc_in32(
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+ &runtime->ifc_nand.nandseq_strt);
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+ ctrl->saved_rregs->ifc_nand.nand_evter_en =
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+ ifc_in32(
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+ &runtime->ifc_nand.nand_evter_en);
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+ ctrl->saved_rregs->ifc_nand.nanndcr =
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+ ifc_in32(&runtime->ifc_nand.nanndcr);
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+ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
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+ ifc_in32(
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+ &runtime->ifc_nand.nand_dll_lowcfg0);
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+ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
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+ ifc_in32(
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+ &runtime->ifc_nand.nand_dll_lowcfg1);
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+
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+ /* IFC controller NOR machine registers */
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+ ctrl->saved_rregs->ifc_nor.nor_evter_en =
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+ ifc_in32(
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+ &runtime->ifc_nor.nor_evter_en);
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+ ctrl->saved_rregs->ifc_nor.norcr =
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+ ifc_in32(&runtime->ifc_nor.norcr);
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+
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+ /* IFC controller GPCM Machine registers */
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+ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
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+ ifc_in32(
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+ &runtime->ifc_gpcm.gpcm_evter_en);
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+ }
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+
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+/* save the interrupt values */
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+ ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
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+ ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
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+ ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
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+ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
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+
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+ return 0;
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+}
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+
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+/* restore ifc registers */
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+static int fsl_ifc_resume(struct device *dev)
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+{
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+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
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+ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
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+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
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+ struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
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+ struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
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+ uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
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+
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+/*
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+ * IFC interrupts disabled
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+ */
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+ ifc_out32(0x0, &fcm->cm_evter_intr_en);
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+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
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+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
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+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
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+
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+
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+ if (ctrl->saved_gregs) {
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+ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
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+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
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+ &fcm->cspr_cs[ifc_bank].cspr_ext);
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+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
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+ &fcm->cspr_cs[ifc_bank].cspr);
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+ ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
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+ &fcm->amask_cs[ifc_bank].amask);
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+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
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+ &fcm->csor_cs[ifc_bank].csor_ext);
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+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
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+ &fcm->csor_cs[ifc_bank].csor);
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+ for (i = 0; i < 4; i++) {
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+ ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
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+ &fcm->ftim_cs[ifc_bank].ftim[i]);
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+ }
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+ }
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+ ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
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+ ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
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+ ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
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+ ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
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+ ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
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+ }
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+
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+ if (ctrl->saved_rregs) {
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+ /* IFC controller NAND machine registers */
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+ ifc_out32(savd_rregs->ifc_nand.ncfgr,
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+ &runtime->ifc_nand.ncfgr);
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+ ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
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+ &runtime->ifc_nand.nand_fcr0);
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+ ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
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+ &runtime->ifc_nand.nand_fcr1);
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+ ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
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+ ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
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+ ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
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+ ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
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+ ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
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+ ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
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+ ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
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+ ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
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+ ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
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+ &runtime->ifc_nand.nand_fbcr);
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+ ifc_out32(savd_rregs->ifc_nand.nand_fir0,
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+ &runtime->ifc_nand.nand_fir0);
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+ ifc_out32(savd_rregs->ifc_nand.nand_fir1,
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+ &runtime->ifc_nand.nand_fir1);
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+ ifc_out32(savd_rregs->ifc_nand.nand_fir2,
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+ &runtime->ifc_nand.nand_fir2);
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+ ifc_out32(savd_rregs->ifc_nand.nand_csel,
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+ &runtime->ifc_nand.nand_csel);
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+ ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
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+ &runtime->ifc_nand.nandseq_strt);
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+ ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
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+ &runtime->ifc_nand.nand_evter_en);
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+ ifc_out32(savd_rregs->ifc_nand.nanndcr,
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+ &runtime->ifc_nand.nanndcr);
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+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
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+ &runtime->ifc_nand.nand_dll_lowcfg0);
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+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
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+ &runtime->ifc_nand.nand_dll_lowcfg1);
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+
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+ /* IFC controller NOR machine registers */
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+ ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
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+ &runtime->ifc_nor.nor_evter_en);
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+ ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
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+
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+ /* IFC controller GPCM Machine registers */
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+ ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
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+ &runtime->ifc_gpcm.gpcm_evter_en);
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+
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+ /* IFC interrupts enabled */
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+ ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
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+ &fcm->cm_evter_intr_en);
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+ ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
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+ &runtime->ifc_nand.nand_evter_intr_en);
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+ ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
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+ &runtime->ifc_nor.nor_evter_intr_en);
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+ ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
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+ &runtime->ifc_gpcm.gpcm_evter_intr_en);
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+
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+ kfree(ctrl->saved_gregs);
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+ kfree(ctrl->saved_rregs);
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+ ctrl->saved_gregs = NULL;
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+ ctrl->saved_rregs = NULL;
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+ }
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+
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+ ver = ifc_in32(&fcm->ifc_rev);
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+ ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
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+ if (ver >= FSL_IFC_V1_3_0) {
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+
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+ ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
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+ &runtime->ifc_nand.ncfgr);
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+ /* wait for SRAM_INIT bit to be clear or timeout */
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+ timeout = 10;
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+ while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
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+ IFC_NAND_SRAM_INIT_EN) && timeout) {
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+ mdelay(IFC_TIMEOUT_MSECS);
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+ timeout--;
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+ }
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+
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+ if (!timeout)
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+ dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
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+ }
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+
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+ return 0;
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+}
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+#endif /* CONFIG_PM_SLEEP */
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+
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static const struct of_device_id fsl_ifc_match[] = {
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{
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.compatible = "fsl,ifc",
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@@ -318,10 +576,15 @@ static const struct of_device_id fsl_ifc
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{},
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};
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+static const struct dev_pm_ops ifc_pm_ops = {
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+ SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
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+};
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+
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static struct platform_driver fsl_ifc_ctrl_driver = {
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.driver = {
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.name = "fsl-ifc",
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.of_match_table = fsl_ifc_match,
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+ .pm = &ifc_pm_ops,
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},
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.probe = fsl_ifc_ctrl_probe,
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.remove = fsl_ifc_ctrl_remove,
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--- a/drivers/mtd/maps/physmap_of.c
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+++ b/drivers/mtd/maps/physmap_of.c
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@@ -20,6 +20,7 @@
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/concat.h>
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+#include <linux/mtd/cfi_endian.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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@@ -209,6 +210,9 @@ static int of_flash_probe(struct platfor
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return err;
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}
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+ if (of_property_read_bool(dp->parent, "big-endian"))
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+ info->list[i].map.swap = CFI_BIG_ENDIAN;
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+
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err = -ENOMEM;
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info->list[i].map.virt = ioremap(info->list[i].map.phys,
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info->list[i].map.size);
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--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -438,7 +438,7 @@ config MTD_NAND_FSL_ELBC
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|
|
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config MTD_NAND_FSL_IFC
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|
tristate "NAND support for Freescale IFC controller"
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- depends on FSL_SOC || ARCH_LAYERSCAPE
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+ depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
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|
select FSL_IFC
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|
select MEMORY
|
|
help
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--- a/drivers/mtd/nand/fsl_ifc_nand.c
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|
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
|
|
@@ -901,7 +901,7 @@ static int fsl_ifc_chip_init(struct fsl_
|
|
chip->ecc.algo = NAND_ECC_HAMMING;
|
|
}
|
|
|
|
- if (ctrl->version == FSL_IFC_VERSION_1_1_0)
|
|
+ if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
|
|
fsl_ifc_sram_init(priv);
|
|
|
|
/*
|
|
--- a/include/linux/fsl_ifc.h
|
|
+++ b/include/linux/fsl_ifc.h
|
|
@@ -274,6 +274,8 @@
|
|
*/
|
|
/* Auto Boot Mode */
|
|
#define IFC_NAND_NCFGR_BOOT 0x80000000
|
|
+/* SRAM INIT EN */
|
|
+#define IFC_NAND_SRAM_INIT_EN 0x20000000
|
|
/* Addressing Mode-ROW0+n/COL0 */
|
|
#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
|
|
/* Addressing Mode-ROW0+n/COL0+n */
|
|
@@ -857,6 +859,11 @@ struct fsl_ifc_ctrl {
|
|
u32 nand_stat;
|
|
wait_queue_head_t nand_wait;
|
|
bool little_endian;
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
+ /*save regs when system goes to deep sleep*/
|
|
+ struct fsl_ifc_global *saved_gregs;
|
|
+ struct fsl_ifc_runtime *saved_rregs;
|
|
+#endif
|
|
};
|
|
|
|
extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
|
|
|