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282 lines
8.2 KiB
282 lines
8.2 KiB
From 3bf30f6381f9287eb99ce096bf2fa327a69c8a71 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Thu, 7 Nov 2013 12:01:48 +0100
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Subject: [PATCH] clocksource: Add Allwinner SoCs HS timers driver
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Most of the Allwinner SoCs (at this time, all but the A10) also have a
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High Speed timers that are not using the 24MHz oscillator as a source
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but rather the AHB clock running much faster.
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The IP is slightly different between the A10s/A13 and the one used in
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the A20/A31, since the latter have 4 timers available, while the former
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have only 2 of them.
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[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
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alphabetically"
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Tested-by: Emilio López <emilio@elopez.com.ar>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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---
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.../bindings/timer/allwinner,sun5i-a13-hstimer.txt | 22 +++
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arch/arm/mach-sunxi/Kconfig | 1 +
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drivers/clocksource/Kconfig | 4 +
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drivers/clocksource/Makefile | 1 +
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drivers/clocksource/timer-sun5i.c | 192 +++++++++++++++++++++
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5 files changed, 220 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
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create mode 100644 drivers/clocksource/timer-sun5i.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
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@@ -0,0 +1,22 @@
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+Allwinner SoCs High Speed Timer Controller
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+
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+Required properties:
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+
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+- compatible : should be "allwinner,sun5i-a13-hstimer" or
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+ "allwinner,sun7i-a20-hstimer"
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+- reg : Specifies base physical address and size of the registers.
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+- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
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+ one)
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+- clocks: phandle to the source clock (usually the AHB clock)
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+
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+Example:
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+
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+timer@01c60000 {
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+ compatible = "allwinner,sun7i-a20-hstimer";
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+ reg = <0x01c60000 0x1000>;
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+ interrupts = <0 51 1>,
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+ <0 52 1>,
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+ <0 53 1>,
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+ <0 54 1>;
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+ clocks = <&ahb1_gates 19>;
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+};
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--- a/arch/arm/mach-sunxi/Kconfig
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+++ b/arch/arm/mach-sunxi/Kconfig
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@@ -13,3 +13,4 @@ config ARCH_SUNXI
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select PINCTRL_SUNXI
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select SPARSE_IRQ
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select SUN4I_TIMER
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+ select SUN5I_HSTIMER
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
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@@ -37,6 +37,10 @@ config SUN4I_TIMER
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select CLKSRC_MMIO
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bool
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+config SUN5I_HSTIMER
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+ select CLKSRC_MMIO
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+ bool
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+
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config VT8500_TIMER
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bool
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--- a/drivers/clocksource/Makefile
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+++ b/drivers/clocksource/Makefile
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@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART) += moxart_time
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obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
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obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
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obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
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+obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
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obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
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obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
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obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o
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--- /dev/null
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+++ b/drivers/clocksource/timer-sun5i.c
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@@ -0,0 +1,192 @@
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+/*
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+ * Allwinner SoCs hstimer driver.
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+ *
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+ * Copyright (C) 2013 Maxime Ripard
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+ *
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+ * Maxime Ripard <maxime.ripard@free-electrons.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/clockchips.h>
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+#include <linux/delay.h>
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+#include <linux/interrupt.h>
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+#include <linux/irq.h>
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+#include <linux/irqreturn.h>
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+#include <linux/sched_clock.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+
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+#define TIMER_IRQ_EN_REG 0x00
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+#define TIMER_IRQ_EN(val) BIT(val)
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+#define TIMER_IRQ_ST_REG 0x04
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+#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
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+#define TIMER_CTL_ENABLE BIT(0)
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+#define TIMER_CTL_RELOAD BIT(1)
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+#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
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+#define TIMER_CTL_ONESHOT BIT(7)
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+#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
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+#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
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+#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
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+#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
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+
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+#define TIMER_SYNC_TICKS 3
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+
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+static void __iomem *timer_base;
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+static u32 ticks_per_jiffy;
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+
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+/*
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+ * When we disable a timer, we need to wait at least for 2 cycles of
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+ * the timer source clock. We will use for that the clocksource timer
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+ * that is already setup and runs at the same frequency than the other
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+ * timers, and we never will be disabled.
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+ */
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+static void sun5i_clkevt_sync(void)
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+{
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+ u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
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+
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+ while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
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+ cpu_relax();
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+}
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+
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+static void sun5i_clkevt_time_stop(u8 timer)
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+{
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+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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+ writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
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+
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+ sun5i_clkevt_sync();
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+}
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+
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+static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
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+{
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+ writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
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+}
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+
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+static void sun5i_clkevt_time_start(u8 timer, bool periodic)
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+{
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+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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+
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+ if (periodic)
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+ val &= ~TIMER_CTL_ONESHOT;
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+ else
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+ val |= TIMER_CTL_ONESHOT;
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+
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+ writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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+ timer_base + TIMER_CTL_REG(timer));
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+}
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+
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+static void sun5i_clkevt_mode(enum clock_event_mode mode,
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+ struct clock_event_device *clk)
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+{
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+ switch (mode) {
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+ case CLOCK_EVT_MODE_PERIODIC:
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+ sun5i_clkevt_time_stop(0);
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+ sun5i_clkevt_time_setup(0, ticks_per_jiffy);
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+ sun5i_clkevt_time_start(0, true);
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+ break;
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+ case CLOCK_EVT_MODE_ONESHOT:
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+ sun5i_clkevt_time_stop(0);
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+ sun5i_clkevt_time_start(0, false);
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+ break;
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+ case CLOCK_EVT_MODE_UNUSED:
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+ case CLOCK_EVT_MODE_SHUTDOWN:
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+ default:
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+ sun5i_clkevt_time_stop(0);
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+ break;
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+ }
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+}
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+
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+static int sun5i_clkevt_next_event(unsigned long evt,
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+ struct clock_event_device *unused)
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+{
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+ sun5i_clkevt_time_stop(0);
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+ sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
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+ sun5i_clkevt_time_start(0, false);
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+
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+ return 0;
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+}
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+
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+static struct clock_event_device sun5i_clockevent = {
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+ .name = "sun5i_tick",
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+ .rating = 340,
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+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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+ .set_mode = sun5i_clkevt_mode,
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+ .set_next_event = sun5i_clkevt_next_event,
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+};
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+
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+
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+static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
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+{
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+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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+
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+ writel(0x1, timer_base + TIMER_IRQ_ST_REG);
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+ evt->event_handler(evt);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction sun5i_timer_irq = {
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+ .name = "sun5i_timer0",
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+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
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+ .handler = sun5i_timer_interrupt,
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+ .dev_id = &sun5i_clockevent,
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+};
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+
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+static u32 sun5i_timer_sched_read(void)
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+{
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+ return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
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+}
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+
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+static void __init sun5i_timer_init(struct device_node *node)
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+{
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+ unsigned long rate;
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+ struct clk *clk;
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+ int ret, irq;
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+ u32 val;
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+
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+ timer_base = of_iomap(node, 0);
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+ if (!timer_base)
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+ panic("Can't map registers");
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+
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+ irq = irq_of_parse_and_map(node, 0);
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+ if (irq <= 0)
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+ panic("Can't parse IRQ");
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+
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+ clk = of_clk_get(node, 0);
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+ if (IS_ERR(clk))
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+ panic("Can't get timer clock");
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+ clk_prepare_enable(clk);
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+ rate = clk_get_rate(clk);
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+
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+ writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
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+ writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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+ timer_base + TIMER_CTL_REG(1));
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+
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+ setup_sched_clock(sun5i_timer_sched_read, 32, rate);
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+ clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
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+ rate, 340, 32, clocksource_mmio_readl_down);
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+
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+ ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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+
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+ ret = setup_irq(irq, &sun5i_timer_irq);
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+ if (ret)
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+ pr_warn("failed to setup irq %d\n", irq);
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+
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+ /* Enable timer0 interrupt */
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+ val = readl(timer_base + TIMER_IRQ_EN_REG);
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+ writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
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+
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+ sun5i_clockevent.cpumask = cpu_possible_mask;
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+ sun5i_clockevent.irq = irq;
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+
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+ clockevents_config_and_register(&sun5i_clockevent, rate,
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+ TIMER_SYNC_TICKS, 0xffffffff);
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+}
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+CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
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+ sun5i_timer_init);
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+CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
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+ sun5i_timer_init);
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