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206 lines
6.0 KiB
206 lines
6.0 KiB
From patchwork Fri Dec 8 09:42:22 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v4,04/12] clk: qcom: Add HFPLL driver
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From: Sricharan R <sricharan@codeaurora.org>
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X-Patchwork-Id: 10102079
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Message-Id: <1512726150-7204-5-git-send-email-sricharan@codeaurora.org>
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To: mturquette@baylibre.com, sboyd@codeaurora.org,
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devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
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linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
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viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
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Cc: sricharan@codeaurora.org
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Date: Fri, 8 Dec 2017 15:12:22 +0530
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From: Stephen Boyd <sboyd@codeaurora.org>
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On some devices (MSM8974 for example), the HFPLLs are
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instantiated within the Krait processor subsystem as separate
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register regions. Add a driver for these PLLs so that we can
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provide HFPLL clocks for use by the system.
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Cc: <devicetree@vger.kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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.../devicetree/bindings/clock/qcom,hfpll.txt | 40 ++++++++
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drivers/clk/qcom/Kconfig | 8 ++
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/hfpll.c | 106 +++++++++++++++++++++
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4 files changed, 155 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
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create mode 100644 drivers/clk/qcom/hfpll.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
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@@ -0,0 +1,40 @@
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+High-Frequency PLL (HFPLL)
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+
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+PROPERTIES
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+
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+- compatible:
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+ Usage: required
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+ Value type: <string>
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+ Definition: must be "qcom,hfpll"
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+
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+- reg:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: address and size of HPLL registers. An optional second
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+ element specifies the address and size of the alias
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+ register region.
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+
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+- clock-output-names:
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+ Usage: required
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+ Value type: <string>
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+ Definition: Name of the PLL. Typically hfpllX where X is a CPU number
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+ starting at 0. Otherwise hfpll_Y where Y is more specific
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+ such as "l2".
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+
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+Example:
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+
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+1) An HFPLL for the L2 cache.
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+
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+ clock-controller@f9016000 {
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+ compatible = "qcom,hfpll";
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+ reg = <0xf9016000 0x30>;
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+ clock-output-names = "hfpll_l2";
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+ };
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+
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+2) An HFPLL for CPU0. This HFPLL has the alias register region.
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+
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+ clock-controller@f908a000 {
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+ compatible = "qcom,hfpll";
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+ reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
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+ clock-output-names = "hfpll0";
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+ };
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -196,3 +196,11 @@ config MSM_MMCC_8996
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Support for the multimedia clock controller on msm8996 devices.
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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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+
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+config QCOM_HFPLL
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+ tristate "High-Frequency PLL (HFPLL) Clock Controller"
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+ depends on COMMON_CLK_QCOM
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+ help
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+ Support for the high-frequency PLLs present on Qualcomm devices.
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+ Say Y if you want to support CPU frequency scaling on devices
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+ such as MSM8974, APQ8084, etc.
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -35,3 +35,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8
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obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
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obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
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obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
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+obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
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--- /dev/null
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+++ b/drivers/clk/qcom/hfpll.c
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@@ -0,0 +1,106 @@
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+/*
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+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/of.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+#include <linux/regmap.h>
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+
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+#include "clk-regmap.h"
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+#include "clk-hfpll.h"
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+
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+static const struct hfpll_data hdata = {
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+ .mode_reg = 0x00,
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+ .l_reg = 0x04,
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+ .m_reg = 0x08,
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+ .n_reg = 0x0c,
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+ .user_reg = 0x10,
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+ .config_reg = 0x14,
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+ .config_val = 0x430405d,
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+ .status_reg = 0x1c,
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+ .lock_bit = 16,
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+
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+ .user_val = 0x8,
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+ .user_vco_mask = 0x100000,
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+ .low_vco_max_rate = 1248000000,
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+ .min_rate = 537600000UL,
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+ .max_rate = 2900000000UL,
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+};
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+
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+static const struct of_device_id qcom_hfpll_match_table[] = {
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+ { .compatible = "qcom,hfpll" },
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+ { }
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+};
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+MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
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+
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+static const struct regmap_config hfpll_regmap_config = {
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+ .reg_bits = 32,
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+ .reg_stride = 4,
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+ .val_bits = 32,
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+ .max_register = 0x30,
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+ .fast_io = true,
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+};
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+
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+static int qcom_hfpll_probe(struct platform_device *pdev)
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+{
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+ struct resource *res;
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+ struct device *dev = &pdev->dev;
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+ void __iomem *base;
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+ struct regmap *regmap;
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+ struct clk_hfpll *h;
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+ struct clk_init_data init = {
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+ .parent_names = (const char *[]){ "xo" },
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+ .num_parents = 1,
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+ .ops = &clk_ops_hfpll,
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+ };
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+
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+ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
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+ if (!h)
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+ return -ENOMEM;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ base = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ if (of_property_read_string_index(dev->of_node, "clock-output-names",
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+ 0, &init.name))
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+ return -ENODEV;
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+
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+ h->d = &hdata;
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+ h->clkr.hw.init = &init;
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+ spin_lock_init(&h->lock);
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+
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+ return devm_clk_register_regmap(&pdev->dev, &h->clkr);
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+}
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+
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+static struct platform_driver qcom_hfpll_driver = {
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+ .probe = qcom_hfpll_probe,
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+ .driver = {
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+ .name = "qcom-hfpll",
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+ .of_match_table = qcom_hfpll_match_table,
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+ },
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+};
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+module_platform_driver(qcom_hfpll_driver);
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+
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+MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
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+MODULE_LICENSE("GPL v2");
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+MODULE_ALIAS("platform:qcom-hfpll");
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