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455 lines
12 KiB
455 lines
12 KiB
From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 30 Nov 2014 14:53:12 +0100
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Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq
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controller
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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.../brcm,bcm6345-periph-intc.txt | 50 +++
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drivers/irqchip/Kconfig | 4 +
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drivers/irqchip/Makefile | 1 +
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drivers/irqchip/irq-bcm6345-periph.c | 339 ++++++++++++++++++++
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include/linux/irqchip/irq-bcm6345-periph.h | 16 +
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5 files changed, 410 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
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create mode 100644 drivers/irqchip/irq-bcm6345-periph.c
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create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
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@@ -0,0 +1,50 @@
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+Broadcom BCM6345 Level 1 periphery interrupt controller
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+
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+This block is a interrupt controller that is typically connected directly
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+to one of the HW INT lines on each CPU. Every BCM63XX xDSL chip since
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+BCM6345 has contained this hardware.
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+
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+Key elements of the hardware design include:
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+
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+- 32, 64, or 128 incoming level IRQ lines
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+
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+- All onchip peripherals are wired directly to an L2 input
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+
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+- A separate instance of the register set for each CPU, allowing individual
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+ peripheral IRQs to be routed to any CPU
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+
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+- No atomic mask/unmask operations
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+
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+- No polarity/level/edge settings
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+
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+- No FIFO or priority encoder logic; software is expected to read all
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+ 1-4 status words to determine which IRQs are pending
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+
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+Required properties:
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+
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+- compatible: Should be "brcm,bcm6345-periph-intc".
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+- reg: Specifies the base physical address and size of the registers.
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+ Multiple register addresses may be specified, and must match the amount of
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+ parent interrupts.
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+- interrupt-controller: Identifies the node as an interrupt controller.
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+- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
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+ source, should be 1.
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+- interrupt-parent: Specifies the phandle to the parent interrupt controller
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+ this one is cascaded from.
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+- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
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+ node, valid values depend on the type of parent interrupt controller.
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+ Multiple lines are used to route interrupts to different cpus, with the first
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+ assumed to be for the boot CPU.
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+
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+Example:
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+
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+periph_intc: interrupt-controller@f0406800 {
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+ compatible = "brcm,bcm6345-periph-intc";
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+ reg = <0x10000020 0x10>, <0x10000030 0x10>;
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+
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ interrupt-parent = <&cpu_intc>;
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+ interrupts = <2>, <3>;
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+};
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--- a/drivers/irqchip/Kconfig
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+++ b/drivers/irqchip/Kconfig
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@@ -110,6 +110,10 @@ config BRCMSTB_L2_IRQ
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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+config BCM6345_PERIPH_IRQ
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+ bool
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+ select IRQ_DOMAIN
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+
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config DW_APB_ICTL
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bool
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select GENERIC_IRQ_CHIP
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--- a/drivers/irqchip/Makefile
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+++ b/drivers/irqchip/Makefile
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@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
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obj-$(CONFIG_IRQ_MXS) += irq-mxs.o
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obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
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obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
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+obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
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obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
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obj-$(CONFIG_METAG) += irq-metag-ext.o
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obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
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--- /dev/null
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+++ b/drivers/irqchip/irq-bcm6345-periph.c
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@@ -0,0 +1,339 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
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+ */
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+
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+#include <linux/ioport.h>
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+#include <linux/irq.h>
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+#include <linux/irqchip.h>
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+#include <linux/irqchip/chained_irq.h>
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+#include <linux/irqchip/irq-bcm6345-periph.h>
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+#include <linux/kernel.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_address.h>
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+#include <linux/slab.h>
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+#include <linux/spinlock.h>
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+
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+#ifdef CONFIG_BCM63XX
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+#include <asm/mach-bcm63xx/bcm63xx_irq.h>
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+
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+#define VIRQ_BASE IRQ_INTERNAL_BASE
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+#else
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+#define VIRQ_BASE 0
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+#endif
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+
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+#define MAX_WORDS 4
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+#define MAX_PARENT_IRQS 2
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+#define IRQS_PER_WORD 32
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+
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+struct intc_block {
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+ int parent_irq;
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+ void __iomem *base;
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+ void __iomem *en_reg[MAX_WORDS];
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+ void __iomem *status_reg[MAX_WORDS];
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+ u32 mask_cache[MAX_WORDS];
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+};
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+
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+struct intc_data {
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+ struct irq_chip chip;
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+ struct intc_block block[MAX_PARENT_IRQS];
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+
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+ int num_words;
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+
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+ struct irq_domain *domain;
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+ raw_spinlock_t lock;
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+};
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+
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+static void bcm6345_periph_irq_handle(struct irq_desc *desc)
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+{
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+ struct intc_data *data = irq_desc_get_handler_data(desc);
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+ struct intc_block *block;
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+ unsigned int irq = irq_desc_get_irq(desc);
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+ unsigned int idx;
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+
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+ chained_irq_enter(chip, desc);
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+
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+ for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
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+ if (irq == data->block[idx].parent_irq)
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+ block = &data->block[idx];
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+
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+ for (idx = 0; idx < data->num_words; idx++) {
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+ int base = idx * IRQS_PER_WORD;
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+ unsigned long pending;
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+ int hw_irq;
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+
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+ raw_spin_lock(&data->lock);
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+ pending = __raw_readl(block->en_reg[idx]) &
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+ __raw_readl(block->status_reg[idx]);
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+ raw_spin_unlock(&data->lock);
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+
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+ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
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+ int virq;
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+
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+ virq = irq_find_mapping(data->domain, base + hw_irq);
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+ generic_handle_irq(virq);
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+ }
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+ }
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+
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+ chained_irq_exit(chip, desc);
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+}
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+
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+static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,
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+ bool enable)
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+{
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+ u32 val;
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+
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+ val = __raw_readl(block->en_reg[reg]);
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+ if (enable)
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+ val |= BIT(bit);
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+ else
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+ val &= ~BIT(bit);
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+ __raw_writel(val, block->en_reg[reg]);
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+}
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+
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+static void bcm6345_periph_irq_mask(struct irq_data *data)
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+{
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+ unsigned int i, reg, bit;
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+ struct intc_data *priv = data->domain->host_data;
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+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
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+
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+ reg = hwirq / IRQS_PER_WORD;
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+ bit = hwirq % IRQS_PER_WORD;
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+
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+ raw_spin_lock(&priv->lock);
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+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
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+ struct intc_block *block = &priv->block[i];
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+
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+ if (!block->parent_irq)
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+ break;
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+
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+ __bcm6345_periph_enable(block, reg, bit, false);
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+ }
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+ raw_spin_unlock(&priv->lock);
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+}
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+
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+static void bcm6345_periph_irq_unmask(struct irq_data *data)
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+{
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+ struct intc_data *priv = data->domain->host_data;
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+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
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+ unsigned int i, reg, bit;
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+
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+ reg = hwirq / IRQS_PER_WORD;
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+ bit = hwirq % IRQS_PER_WORD;
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+
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+ raw_spin_lock(&priv->lock);
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+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
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+ struct intc_block *block = &priv->block[i];
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+
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+ if (!block->parent_irq)
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+ break;
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+
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+ if (block->mask_cache[reg] & BIT(bit))
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+ __bcm6345_periph_enable(block, reg, bit, true);
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+ else
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+ __bcm6345_periph_enable(block, reg, bit, false);
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+ }
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+ raw_spin_unlock(&priv->lock);
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+}
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+
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+#ifdef CONFIG_SMP
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+static int bcm6345_periph_set_affinity(struct irq_data *data,
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+ const struct cpumask *mask, bool force)
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+{
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+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
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+ struct intc_data *priv = data->domain->host_data;
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+ unsigned int i, reg, bit;
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+ unsigned long flags;
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+ bool enabled;
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+ int cpu;
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+
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+ reg = hwirq / IRQS_PER_WORD;
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+ bit = hwirq % IRQS_PER_WORD;
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+
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+ /* we could route to more than one cpu, but performance
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+ suffers, so fix it to one.
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+ */
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+ cpu = cpumask_any_and(mask, cpu_online_mask);
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+ if (cpu >= nr_cpu_ids)
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+ return -EINVAL;
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+
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+ if (cpu >= MAX_PARENT_IRQS)
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+ return -EINVAL;
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+
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+ if (!priv->block[cpu].parent_irq)
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+ return -EINVAL;
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+
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+ raw_spin_lock_irqsave(&priv->lock, flags);
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+ enabled = !irqd_irq_masked(data);
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+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
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+ struct intc_block *block = &priv->block[i];
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+
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+ if (!block->parent_irq)
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+ break;
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+
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+ if (i == cpu) {
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+ block->mask_cache[reg] |= BIT(bit);
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+ __bcm6345_periph_enable(block, reg, bit, enabled);
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+ } else {
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+ block->mask_cache[reg] &= ~BIT(bit);
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+ __bcm6345_periph_enable(block, reg, bit, false);
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+ }
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+ }
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+ raw_spin_unlock_irqrestore(&priv->lock, flags);
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+
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+ return 0;
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+}
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+#endif
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+
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+static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+{
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+ struct intc_data *priv = d->host_data;
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+
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+ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops bcm6345_periph_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = bcm6345_periph_map,
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+};
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+
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+static int __init __bcm6345_periph_intc_init(struct device_node *node,
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+ int num_blocks, int *irq,
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+ void __iomem **base, int num_words)
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+{
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+ struct intc_data *data;
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+ unsigned int i, w, status_offset;
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+
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+ data = kzalloc(sizeof(*data), GFP_KERNEL);
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+ if (!data)
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+ return -ENOMEM;
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+
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+ raw_spin_lock_init(&data->lock);
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+
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+ status_offset = num_words * sizeof(u32);
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+
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+ for (i = 0; i < num_blocks; i++) {
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+ struct intc_block *block = &data->block[i];
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+
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+ block->parent_irq = irq[i];
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+ block->base = base[i];
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+
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+ for (w = 0; w < num_words; w++) {
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+ int word_offset = sizeof(u32) * ((num_words - w) - 1);
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+
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+ block->en_reg[w] = base[i] + word_offset;
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+ block->status_reg[w] = base[i] + status_offset;
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+ block->status_reg[w] += word_offset;
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+
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+ /* route all interrupts to line 0 by default */
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+ if (i == 0)
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+ block->mask_cache[w] = 0xffffffff;
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+ }
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+
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+ irq_set_handler_data(block->parent_irq, data);
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+ irq_set_chained_handler(block->parent_irq,
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+ bcm6345_periph_irq_handle);
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+ }
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+
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+ data->num_words = num_words;
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+
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+ data->chip.name = "bcm6345-periph-intc";
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+ data->chip.irq_mask = bcm6345_periph_irq_mask;
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+ data->chip.irq_unmask = bcm6345_periph_irq_unmask;
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+
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+#ifdef CONFIG_SMP
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+ if (num_blocks > 1)
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+ data->chip.irq_set_affinity = bcm6345_periph_set_affinity;
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+#endif
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+
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+ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
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+ VIRQ_BASE,
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+ &bcm6345_periph_domain_ops, data);
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+ if (!data->domain) {
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+ kfree(data);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+void __init bcm6345_periph_intc_init(int num_blocks, int *irq,
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+ void __iomem **base, int num_words)
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+{
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+ __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);
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+}
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+
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+#ifdef CONFIG_OF
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+static int __init bcm6345_periph_of_init(struct device_node *node,
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+ struct device_node *parent)
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+{
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+ struct resource res;
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+ int num_irqs, ret = -EINVAL;
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+ int irqs[MAX_PARENT_IRQS] = { 0 };
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+ void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
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+ int words = 0;
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+ int i;
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+
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+ num_irqs = of_irq_count(node);
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+
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+ if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
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+ return -EINVAL;
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+
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+ for (i = 0; i < num_irqs; i++) {
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+ resource_size_t size;
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+
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+ irqs[i] = irq_of_parse_and_map(node, i);
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+ if (!irqs[i])
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+ goto out_unmap;
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+
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+ if (of_address_to_resource(node, i, &res))
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+ goto out_unmap;
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+
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+ size = resource_size(&res);
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+ switch (size) {
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+ case 8:
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+ case 16:
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+ case 32:
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+ size = size / 8;
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+ break;
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+ default:
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+ goto out_unmap;
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+ }
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+
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+ if (words && words != size) {
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+ ret = -EINVAL;
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+ goto out_unmap;
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+ }
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+ words = size;
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+
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+ bases[i] = of_iomap(node, i);
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+ if (!bases[i]) {
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+ ret = -ENOMEM;
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+ goto out_unmap;
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+ }
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+ }
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+
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+ ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);
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+ if (!ret)
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+ return 0;
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+
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+out_unmap:
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+ for (i = 0; i < num_irqs; i++) {
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+ iounmap(bases[i]);
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+ irq_dispose_mapping(irqs[i]);
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+ }
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+
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+ return ret;
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+}
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+
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+IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-l1-intc",
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+ bcm6345_periph_of_init);
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+#endif
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--- /dev/null
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+++ b/include/linux/irqchip/irq-bcm6345-periph.h
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@@ -0,0 +1,16 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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+ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
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+ */
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+
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+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
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+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
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+
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+void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,
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+ int num_words);
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+
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+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */
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