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334 lines
10 KiB
334 lines
10 KiB
--- a/drivers/net/ethernet/qualcomm/essedma/edma.c
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
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@@ -161,8 +161,10 @@ static void edma_configure_rx(struct edm
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/* Set Rx FIFO threshold to start to DMA data to host */
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rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE;
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+ if (!edma_cinfo->is_single_phy) {
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/* Set RX remove vlan bit */
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rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN;
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+ }
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edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data);
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}
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@@ -1293,6 +1295,10 @@ void edma_adjust_link(struct net_device
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if (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) {
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dev_info(&adapter->pdev->dev, "%s: GMAC Link is up with phy_speed=%d\n", netdev->name, phydev->speed);
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adapter->link_state = __EDMA_LINKUP;
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+ if (adapter->edma_cinfo->is_single_phy) {
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+ ess_set_port_status_speed(adapter->edma_cinfo, phydev,
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+ ffs(adapter->dp_bitmap) - 1);
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+ }
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netif_carrier_on(netdev);
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if (netif_running(netdev))
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netif_tx_wake_all_queues(netdev);
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@@ -1386,10 +1392,12 @@ netdev_tx_t edma_xmit(struct sk_buff *sk
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}
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/* Check and mark VLAN tag offload */
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- if (skb_vlan_tag_present(skb))
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- flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
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- else if (adapter->default_vlan_tag)
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- flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
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+ if (!adapter->edma_cinfo->is_single_phy) {
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+ if (unlikely(skb_vlan_tag_present(skb)))
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+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
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+ else if (adapter->default_vlan_tag)
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+ flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
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+ }
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/* Check and mark checksum offload */
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if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
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--- a/drivers/net/ethernet/qualcomm/essedma/edma.h
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma.h
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@@ -31,6 +31,7 @@
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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+#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/sysctl.h>
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@@ -332,6 +333,9 @@ struct edma_common_info {
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struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
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spinlock_t stats_lock; /* protect edma stats area for updation */
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struct timer_list edma_stats_timer;
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+ bool is_single_phy;
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+ void __iomem *ess_hw_addr;
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+ struct clk *ess_clk;
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};
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/* transimit packet descriptor (tpd) ring */
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@@ -444,4 +448,6 @@ void edma_change_tx_coalesce(int usecs);
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void edma_change_rx_coalesce(int usecs);
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void edma_get_tx_rx_coalesce(u32 *reg_val);
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void edma_clear_irq_status(void);
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+void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
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+ struct phy_device *phydev, uint8_t port_id);
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#endif /* _EDMA_H_ */
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--- a/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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+++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
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@@ -17,6 +17,11 @@
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#include <linux/of.h>
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#include <linux/of_net.h>
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#include <linux/timer.h>
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+#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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+#include <linux/clk.h>
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+#include <linux/string.h>
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+#include <linux/reset.h>
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#include "edma.h"
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#include "ess_edma.h"
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@@ -81,6 +86,101 @@ void edma_read_reg(u16 reg_addr, volatil
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*reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr));
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}
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+static void ess_write_reg(struct edma_common_info *edma, u16 reg_addr, u32 reg_value)
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+{
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+ writel(reg_value, ((void __iomem *)
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+ ((unsigned long)edma->ess_hw_addr + reg_addr)));
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+}
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+
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+static void ess_read_reg(struct edma_common_info *edma, u16 reg_addr,
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+ volatile u32 *reg_value)
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+{
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+ *reg_value = readl((void __iomem *)
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+ ((unsigned long)edma->ess_hw_addr + reg_addr));
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+}
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+
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+static int ess_reset(struct edma_common_info *edma)
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+{
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+ struct device_node *switch_node = NULL;
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+ struct reset_control *ess_rst;
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+ u32 regval;
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+
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+ switch_node = of_find_node_by_name(NULL, "ess-switch");
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+ if (!switch_node) {
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+ pr_err("switch-node not found\n");
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+ return -EINVAL;
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+ }
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+
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+ ess_rst = of_reset_control_get(switch_node, "ess_rst");
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+ of_node_put(switch_node);
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+
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+ if (IS_ERR(ess_rst)) {
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+ pr_err("failed to find ess_rst!\n");
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+ return -ENOENT;
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+ }
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+
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+ reset_control_assert(ess_rst);
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+ msleep(10);
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+ reset_control_deassert(ess_rst);
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+ msleep(100);
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+ reset_control_put(ess_rst);
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+
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+ /* Enable only port 5 <--> port 0
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+ * bits 0:6 bitmap of ports it can fwd to */
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+#define SET_PORT_BMP(r,v) \
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+ ess_read_reg(edma, r, ®val); \
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+ ess_write_reg(edma, r, ((regval & ~0x3F) | v));
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+
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+ SET_PORT_BMP(ESS_PORT0_LOOKUP_CTRL,0x20);
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+ SET_PORT_BMP(ESS_PORT1_LOOKUP_CTRL,0x00);
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+ SET_PORT_BMP(ESS_PORT2_LOOKUP_CTRL,0x00);
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+ SET_PORT_BMP(ESS_PORT3_LOOKUP_CTRL,0x00);
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+ SET_PORT_BMP(ESS_PORT4_LOOKUP_CTRL,0x00);
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+ SET_PORT_BMP(ESS_PORT5_LOOKUP_CTRL,0x01);
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+ ess_write_reg(edma, ESS_RGMII_CTRL, 0x400);
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+ ess_write_reg(edma, ESS_PORT0_STATUS, ESS_PORT_1G_FDX);
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+ ess_write_reg(edma, ESS_PORT5_STATUS, ESS_PORT_1G_FDX);
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+ ess_write_reg(edma, ESS_PORT0_HEADER_CTRL, 0);
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+#undef SET_PORT_BMP
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+
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+ /* forward multicast and broadcast frames to CPU */
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+ ess_write_reg(edma, ESS_FWD_CTRL1,
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+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_UC_FLOOD_S) |
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+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_MC_FLOOD_S) |
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+ (ESS_PORTS_ALL << ESS_FWD_CTRL1_BC_FLOOD_S));
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+
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+ return 0;
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+}
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+
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+void ess_set_port_status_speed(struct edma_common_info *edma,
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+ struct phy_device *phydev, uint8_t port_id)
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+{
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+ uint16_t reg_off = ESS_PORT0_STATUS + (4 * port_id);
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+ uint32_t reg_val = 0;
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+
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+ ess_read_reg(edma, reg_off, ®_val);
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+
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+ /* reset the speed bits [0:1] */
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+ reg_val &= ~ESS_PORT_STATUS_SPEED_INV;
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+
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+ /* set the new speed */
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+ switch(phydev->speed) {
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+ case SPEED_1000: reg_val |= ESS_PORT_STATUS_SPEED_1000; break;
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+ case SPEED_100: reg_val |= ESS_PORT_STATUS_SPEED_100; break;
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+ case SPEED_10: reg_val |= ESS_PORT_STATUS_SPEED_10; break;
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+ default: reg_val |= ESS_PORT_STATUS_SPEED_INV; break;
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+ }
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+
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+ /* check full/half duplex */
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+ if (phydev->duplex) {
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+ reg_val |= ESS_PORT_STATUS_DUPLEX_MODE;
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+ } else {
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+ reg_val &= ~ESS_PORT_STATUS_DUPLEX_MODE;
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+ }
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+
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+ ess_write_reg(edma, reg_off, reg_val);
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+}
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+
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/* edma_change_tx_coalesce()
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* change tx interrupt moderation timer
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*/
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@@ -550,6 +650,31 @@ static struct ctl_table edma_table[] = {
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{}
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};
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+static int ess_parse(struct edma_common_info *edma)
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+{
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+ struct device_node *switch_node;
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+ int ret = -EINVAL;
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+
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+ switch_node = of_find_node_by_name(NULL, "ess-switch");
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+ if (!switch_node) {
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+ pr_err("cannot find ess-switch node\n");
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+ goto out;
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+ }
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+
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+ edma->ess_hw_addr = of_io_request_and_map(switch_node,
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+ 0, KBUILD_MODNAME);
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+ if (!edma->ess_hw_addr) {
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+ pr_err("%s ioremap fail.", __func__);
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+ goto out;
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+ }
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+
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+ edma->ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
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+ ret = clk_prepare_enable(edma->ess_clk);
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+out:
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+ of_node_put(switch_node);
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+ return ret;
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+}
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+
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/* edma_axi_netdev_ops
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* Describe the operations supported by registered netdevices
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*
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@@ -785,6 +910,17 @@ static int edma_axi_probe(struct platfor
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miibus = mdio_data->mii_bus;
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}
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+ if (of_property_read_bool(np, "qcom,single-phy") &&
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+ edma_cinfo->num_gmac == 1) {
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+ err = ess_parse(edma_cinfo);
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+ if (!err)
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+ err = ess_reset(edma_cinfo);
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+ if (err)
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+ goto err_single_phy_init;
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+ else
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+ edma_cinfo->is_single_phy = true;
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+ }
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+
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for_each_available_child_of_node(np, pnp) {
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const char *mac_addr;
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@@ -1073,11 +1209,15 @@ static int edma_axi_probe(struct platfor
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for (i = 0; i < edma_cinfo->num_gmac; i++) {
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if (adapter[i]->poll_required) {
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+ int phy_mode = of_get_phy_mode(np);
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+
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+ if (phy_mode < 0)
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+ phy_mode = PHY_INTERFACE_MODE_SGMII;
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adapter[i]->phydev =
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phy_connect(edma_netdev[i],
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(const char *)adapter[i]->phy_id,
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&edma_adjust_link,
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- PHY_INTERFACE_MODE_SGMII);
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+ phy_mode);
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if (IS_ERR(adapter[i]->phydev)) {
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dev_dbg(&pdev->dev, "PHY attach FAIL");
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err = -EIO;
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@@ -1121,6 +1261,9 @@ err_rmap_alloc_fail:
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for (i = 0; i < edma_cinfo->num_gmac; i++)
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unregister_netdev(edma_netdev[i]);
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err_register:
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+err_single_phy_init:
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+ iounmap(edma_cinfo->ess_hw_addr);
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+ clk_disable_unprepare(edma_cinfo->ess_clk);
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err_mdiobus_init_fail:
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edma_free_rx_rings(edma_cinfo);
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err_rx_rinit:
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@@ -1181,6 +1324,8 @@ static int edma_axi_remove(struct platfo
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del_timer_sync(&edma_cinfo->edma_stats_timer);
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edma_free_irqs(adapter);
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unregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr);
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+ iounmap(edma_cinfo->ess_hw_addr);
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+ clk_disable_unprepare(edma_cinfo->ess_clk);
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edma_free_tx_resources(edma_cinfo);
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edma_free_rx_resources(edma_cinfo);
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edma_free_tx_rings(edma_cinfo);
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--- a/drivers/net/ethernet/qualcomm/essedma/ess_edma.h
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+++ b/drivers/net/ethernet/qualcomm/essedma/ess_edma.h
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@@ -329,4 +329,61 @@ struct edma_hw;
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#define EDMA_RRD_PRIORITY_MASK 0x7
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#define EDMA_RRD_PORT_TYPE_SHIFT 7
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#define EDMA_RRD_PORT_TYPE_MASK 0x1F
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+
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+#define ESS_RGMII_CTRL 0x0004
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+
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+/* Port status registers */
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+#define ESS_PORT0_STATUS 0x007C
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+#define ESS_PORT1_STATUS 0x0080
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+#define ESS_PORT2_STATUS 0x0084
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+#define ESS_PORT3_STATUS 0x0088
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+#define ESS_PORT4_STATUS 0x008C
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+#define ESS_PORT5_STATUS 0x0090
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+
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+#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80
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+#define ESS_PORT_STATUS_DUPLEX_MODE 0x40
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+#define ESS_PORT_STATUS_RX_FLOW_EN 0x20
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+#define ESS_PORT_STATUS_TX_FLOW_EN 0x10
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+#define ESS_PORT_STATUS_RX_MAC_EN 0x08
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+#define ESS_PORT_STATUS_TX_MAC_EN 0x04
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+#define ESS_PORT_STATUS_SPEED_INV 0x03
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+#define ESS_PORT_STATUS_SPEED_1000 0x02
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+#define ESS_PORT_STATUS_SPEED_100 0x01
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+#define ESS_PORT_STATUS_SPEED_10 0x00
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+
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+#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
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+ ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \
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+ ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000)
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+
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+#define PHY_STATUS_REG 0x11
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+#define PHY_STATUS_SPEED 0xC000
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+#define PHY_STATUS_SPEED_SHIFT 14
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+#define PHY_STATUS_DUPLEX 0x2000
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+#define PHY_STATUS_DUPLEX_SHIFT 13
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+#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
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+#define PHY_STATUS_CARRIER 0x0400
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+#define PHY_STATUS_CARRIER_SHIFT 10
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+
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+/* Port lookup control registers */
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+#define ESS_PORT0_LOOKUP_CTRL 0x0660
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+#define ESS_PORT1_LOOKUP_CTRL 0x066C
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+#define ESS_PORT2_LOOKUP_CTRL 0x0678
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+#define ESS_PORT3_LOOKUP_CTRL 0x0684
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+#define ESS_PORT4_LOOKUP_CTRL 0x0690
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+#define ESS_PORT5_LOOKUP_CTRL 0x069C
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+
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+#define ESS_PORT0_HEADER_CTRL 0x009C
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+
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+#define ESS_PORTS_ALL 0x3f
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+
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+#define ESS_FWD_CTRL1 0x0624
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+#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7)
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+#define ESS_FWD_CTRL1_UC_FLOOD_S 0
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+#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7)
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+#define ESS_FWD_CTRL1_MC_FLOOD_S 8
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+#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7)
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+#define ESS_FWD_CTRL1_BC_FLOOD_S 16
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+#define ESS_FWD_CTRL1_IGMP BITS(24, 7)
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+#define ESS_FWD_CTRL1_IGMP_S 24
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+
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#endif /* _ESS_EDMA_H_ */
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