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540 lines
15 KiB
540 lines
15 KiB
From b4ac5820bdc98ee24a2f73b8bd7fdf7f82db3a46 Mon Sep 17 00:00:00 2001
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From: Marko Ratkaj <marko.ratkaj@sartura.hr>
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Date: Fri, 7 Apr 2017 11:02:30 +0200
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Subject: [PATCH 2/2] add ClearFog Base device tree files
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Signed-off-by: Marko Ratkaj <marko.ratkaj@sartura.hr>
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/armada-388-clearfog-base.dts | 161 ++++++++++++
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arch/arm/boot/dts/armada-388-clearfog.dtsi | 282 +++++++++++++++++++++
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.../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 +++++
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4 files changed, 506 insertions(+)
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create mode 100644 arch/arm/boot/dts/armada-388-clearfog-base.dts
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create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dtsi
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create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -925,6 +925,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
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armada-385-linksys-shelby.dtb \
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armada-388-clearfog.dtb \
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armada-388-clearfog-pro.dtb \
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+ armada-388-clearfog-base.dtb \
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armada-388-db.dtb \
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armada-388-gp.dtb \
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armada-388-rd.dtb
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--- /dev/null
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+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
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@@ -0,0 +1,161 @@
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+/*
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+ * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
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+ *
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+ * Copyright (C) 2015 Russell King
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+ *
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+ * This board is in development; the contents of this file work with
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+ * the A1 rev 2.0 of the board, which does not represent final
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+ * production board. Things will change, don't expect this file to
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+ * remain compatible info the future.
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This file is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * version 2 as published by the Free Software Foundation.
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+ *
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+ * This file is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/dts-v1/;
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+#include "armada-388-clearfog.dtsi"
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+#include "armada-38x-solidrun-microsom-emmc.dtsi"
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+
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+/ {
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+ model = "SolidRun Clearfog Base A1";
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+ compatible = "solidrun,clearfog-base-a1",
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+ "solidrun,clearfog-a1", "marvell,armada388",
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+ "marvell,armada385", "marvell,armada380";
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ pinctrl-0 = <&rear_button_pins>;
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+ pinctrl-names = "default";
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+
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+ button_0 {
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+ /* The rear SW3 button */
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+ label = "Rear Button";
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+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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+ linux,can-disable;
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+ linux,code = <BTN_0>;
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+ };
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+ };
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+};
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+
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+ð1 {
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+ phy = <&phy1>;
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+};
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+
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+&gpio0 {
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+ phy1_reset {
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+ gpio-hog;
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+ gpios = <19 GPIO_ACTIVE_LOW>;
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+ output-low;
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+ line-name = "phy1-reset";
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+ };
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+};
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+
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+&mdio {
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+ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>;
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+ phy1: ethernet-phy@1 {
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+ /*
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+ * Annoyingly, the marvell phy driver configures the LED
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+ * register, rather than preserving reset-loaded setting.
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+ * We undo that rubbish here.
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+ */
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+ marvell,reg-init = <3 16 0 0x101e>;
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+ reg = <1>;
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+ };
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+};
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+
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+&pinctrl {
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+ /* phy1 reset */
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+ clearfog_phy_pins: clearfog-phy-pins {
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+ marvell,pins = "mpp19";
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+ marvell,function = "gpio";
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+ };
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+ rear_button_pins: rear-button-pins {
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+ marvell,pins = "mpp44";
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+ marvell,function = "gpio";
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+ };
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+};
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+
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+/*
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+MPP
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+18: pu gpio pca9655 int
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+19: gpio phy reset
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+20: pu gpio sd0 detect
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+21: sd0:cmd
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+22: pd gpio mikro int
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+23:
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+
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+24: ua1:rxd mikro rx
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+25: ua1:txd mikro tx
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+26: pu i2c1:sck
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+27: pu i2c1:sda
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+28: sd0:clk
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+29: pd gpio mikro rst
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+30:
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+31:
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+
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+32:
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+33:
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+34:
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+35:
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+36:
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+37: sd0:d3
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+38: sd0:d0
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+39: sd0:d1
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+
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+40: sd0:d2
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+41:
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+42:
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+43: spi1:cs2 mikro cs
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+44: gpio rear button sw3
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+45: ref:clk_out0 phy#0 clock
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+46: ref:clk_out1 phy#1 clock
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+47:
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+
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+48: gpio J18 spare gpio
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+49: gpio U10 I2C_IRQ(GNSS)
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+50: gpio board id?
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+51:
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+52:
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+53:
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+54: gpio mikro pwm
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+55:
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+
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+56: pu spi1:mosi mikro mosi
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+57: pd spi1:sck mikro sck
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+58: spi1:miso mikro miso
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+59:
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+*/
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--- /dev/null
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+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
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@@ -0,0 +1,282 @@
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+/*
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+ * Device Tree include file for SolidRun Clearfog 88F6828 based boards
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+ *
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+ * Copyright (C) 2015 Russell King
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+ *
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+ * This board is in development; the contents of this file work with
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+ * the A1 rev 2.0 of the board, which does not represent final
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+ * production board. Things will change, don't expect this file to
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+ * remain compatible info the future.
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This file is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * version 2 as published by the Free Software Foundation.
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+ *
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+ * This file is distributed in the hope that it will be useful
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+#include "armada-388.dtsi"
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+#include "armada-38x-solidrun-microsom.dtsi"
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+
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+/ {
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+ aliases {
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+ /* So that mvebu u-boot can update the MAC addresses */
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+ ethernet1 = ð0;
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+ ethernet2 = ð1;
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+ ethernet3 = ð2;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "3P3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ };
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+
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+ soc {
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+ internal-regs {
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+ sata@a8000 {
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+ /* pinctrl? */
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+ status = "okay";
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+ };
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+
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+ sata@e0000 {
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+ /* pinctrl? */
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+ status = "okay";
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+ };
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+
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+ sdhci@d8000 {
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+ bus-width = <4>;
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+ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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+ no-1-8-v;
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+ pinctrl-0 = <µsom_sdhci_pins
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+ &clearfog_sdhci_cd_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+ vmmc = <®_3p3v>;
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+ wp-inverted;
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+ };
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+
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+ usb@58000 {
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+ /* CON3, nearest power. */
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+ status = "okay";
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+ };
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+
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+ usb3@f8000 {
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+ /* CON7 */
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+ status = "okay";
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+ };
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+ };
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+
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+ pcie-controller {
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+ status = "okay";
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+ /*
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+ * The two PCIe units are accessible through
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+ * the mini-PCIe connectors on the board.
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+ */
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+ pcie@2,0 {
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+ /* Port 1, Lane 0. CON3, nearest power. */
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+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+ };
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+ };
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+ };
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+
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+ sfp: sfp {
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+ compatible = "sff,sfp";
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+ i2c-bus = <&i2c1>;
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+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
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+ moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
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+ sfp,ethernet = <ð2>;
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+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
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+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
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+ };
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+};
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+
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+ð1 {
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+ /* ethernet@30000 */
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+ bm,pool-long = <2>;
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+ bm,pool-short = <1>;
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+ buffer-manager = <&bm>;
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+ phy-mode = "sgmii";
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+ status = "okay";
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+};
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+
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+ð2 {
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+ /* ethernet@34000 */
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+ bm,pool-long = <3>;
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+ bm,pool-short = <1>;
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+ buffer-manager = <&bm>;
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+ managed = "in-band-status";
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+ phy-mode = "sgmii";
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ clock-frequency = <400000>;
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+ pinctrl-0 = <&i2c0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ /*
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+ * PCA9655 GPIO expander, up to 1MHz clock.
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+ * 0-CON3 CLKREQ#
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+ * 1-CON3 PERST#
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+ * 2-
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+ * 3-CON3 W_DISABLE
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+ * 4-
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+ * 5-USB3 overcurrent
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+ * 6-USB3 power
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+ * 7-
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+ * 8-JP4 P1
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+ * 9-JP4 P4
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+ * 10-JP4 P5
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+ * 11-m.2 DEVSLP
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+ * 12-SFP_LOS
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+ * 13-SFP_TX_FAULT
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+ * 14-SFP_TX_DISABLE
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+ * 15-SFP_MOD_DEF0
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+ */
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+ expander0: gpio-expander@20 {
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+ /*
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+ * This is how it should be:
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+ * compatible = "onnn,pca9655", "nxp,pca9555";
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+ * but you can't do this because of the way I2C works.
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+ */
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+ compatible = "nxp,pca9555";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ reg = <0x20>;
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+
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+ pcie1_0_clkreq {
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+ gpio-hog;
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+ gpios = <0 GPIO_ACTIVE_LOW>;
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+ input;
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+ line-name = "pcie1.0-clkreq";
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+ };
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+ pcie1_0_w_disable {
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+ gpio-hog;
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+ gpios = <3 GPIO_ACTIVE_LOW>;
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+ output-low;
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+ line-name = "pcie1.0-w-disable";
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+ };
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+ usb3_ilimit {
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+ gpio-hog;
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+ gpios = <5 GPIO_ACTIVE_LOW>;
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+ input;
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+ line-name = "usb3-current-limit";
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+ };
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+ usb3_power {
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+ gpio-hog;
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+ gpios = <6 GPIO_ACTIVE_HIGH>;
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+ output-high;
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+ line-name = "usb3-power";
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+ };
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+ m2_devslp {
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+ gpio-hog;
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+ gpios = <11 GPIO_ACTIVE_HIGH>;
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+ output-low;
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+ line-name = "m.2 devslp";
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+ };
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+ };
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+
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+ /* The MCP3021 supports standard and fast modes */
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+ mikrobus_adc: mcp3021@4c {
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+ compatible = "microchip,mcp3021";
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+ reg = <0x4c>;
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+ };
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+};
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+
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+&i2c1 {
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+ /*
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+ * Routed to SFP, mikrobus, and PCIe.
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+ * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
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+ * address pins tied low, which takes addresses 0x50 and 0x51.
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+ * Mikrobus doesn't specify beyond an I2C bus being present.
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+ * PCIe uses ARP to assign addresses, or 0x63-0x64.
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+ */
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+ clock-frequency = <100000>;
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+ pinctrl-0 = <&clearfog_i2c1_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&pinctrl {
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+ clearfog_i2c1_pins: i2c1-pins {
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+ /* SFP, PCIe, mSATA, mikrobus */
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+ marvell,pins = "mpp26", "mpp27";
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+ marvell,function = "i2c1";
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+ };
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+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
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+ marvell,pins = "mpp20";
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+ marvell,function = "gpio";
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+ };
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+ mikro_pins: mikro-pins {
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+ /* int: mpp22 rst: mpp29 */
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+ marvell,pins = "mpp22", "mpp29";
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+ marvell,function = "gpio";
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+ };
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+ mikro_spi_pins: mikro-spi-pins {
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+ marvell,pins = "mpp43";
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+ marvell,function = "spi1";
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+ };
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+ mikro_uart_pins: mikro-uart-pins {
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+ marvell,pins = "mpp24", "mpp25";
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+ marvell,function = "ua1";
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+ };
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+};
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+
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+&spi1 {
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+ /*
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+ * Add SPI CS pins for clearfog:
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+ * CS0: W25Q32 (not populated on uSOM)
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+ * CS1: PIC microcontroller (Pro models)
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+ * CS2: mikrobus
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+ */
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+ pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ /* mikrobus uart */
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+ pinctrl-0 = <&mikro_uart_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
|
@@ -0,0 +1,62 @@
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+/*
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+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
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+ *
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+ * Copyright (C) 2015 Russell King
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+ *
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+ * This board is in development; the contents of this file work with
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+ * the A1 rev 2.0 of the board, which does not represent final
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+ * production board. Things will change, don't expect this file to
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+ * remain compatible info the future.
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This file is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * version 2 as published by the Free Software Foundation.
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+ *
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+ * This file is distributed in the hope that it will be useful
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+/ {
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+ soc {
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+ internal-regs {
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+ sdhci@d8000 {
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+ bus-width = <4>;
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+ no-1-8-v;
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+ non-removable;
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+ pinctrl-0 = <µsom_sdhci_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+ wp-inverted;
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+ };
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+ };
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+ };
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+};
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